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Tue, 16 Jun 2026 07:05:47 -0700 (PDT) X-Received: by 2002:a05:6102:f07:b0:631:2be3:b6e8 with SMTP id ada2fe7eead31-71e88dd8cd2mr2916747137.6.1781618747389; Tue, 16 Jun 2026 07:05:47 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bfe5116f409sm620047966b.23.2026.06.16.07.05.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jun 2026 07:05:46 -0700 (PDT) Message-ID: <1bbccb16-b91e-4116-a4cd-213a46978fa1@oss.qualcomm.com> Date: Tue, 16 Jun 2026 16:05:43 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers To: Qiang Yu , Dmitry Baryshkov Cc: Manivannan Sadhasivam , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> <20260518-link_mode_0519-v4-5-269cd73cc5d1@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE2MDE0MyBTYWx0ZWRfX3dTkMMVh0gWp Xmw445VjSjT4/DU0E5TD11zlQde5l8oRj9mIN0KFnJn/WEc5MHeFwxbZlkytWoF9WTMdsYbIyHM BAJsvpVE7txSxunaUpupqJKGpR7QY4U= X-Proofpoint-GUID: i3oV3YkNCxJQJli7JolBrWh1EO0aCMH5 X-Authority-Analysis: v=2.4 cv=DoZmPm/+ c=1 sm=1 tr=0 ts=6a31583c cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=w-i5jriU0KAIvmwf_0wA:9 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-ORIG-GUID: i3oV3YkNCxJQJli7JolBrWh1EO0aCMH5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE2MDE0MyBTYWx0ZWRfX27/VxTBbuxvS aLkzJbi0YbAUTvinCJYfRuN3T5Tv7J5C0D8NaP2YaTdbuUmdhE1nFOBz99uTY1tSreozogrBz2S BBkCTVQAvsOEK7DUmWfJEysznZtx/UG28lwAHSOJjBDLijvovhHhefSJQzlkmo63oXZXk/jIZ8f tbMsddyyAYhRpTjsg0YIdaJ9ZxhRrF9TVn7r7M7UK1pxRy48VaJgfHOUTafKXdoFOAbb5IV8LpT ps3CDkiwu9f9KMMRUdnuOQbmlXpIZXlao3PM5e68oZrKsgpxMWxtrkRLDYanuvEHPVcTNApPKZr QCJdqj1tmizPFsciiDaBFem1+mAupB2mREqesKGtnXI2wEvzO29lQwAEA8d0n1MUMOR878uFoYh rymP+mcFRIjJo7JbV3gNSi9iRqjkeKKSDAQ1OBlHsC3gGo4D9oaI3UUa0HWlUKJxjSNd0TZUzDC vk4b7zY9Hyh2W3QcQRQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_04,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606160143 On 5/29/26 9:02 AM, Qiang Yu wrote: > On Thu, May 28, 2026 at 04:48:24PM +0300, Dmitry Baryshkov wrote: >> On Fri, May 22, 2026 at 04:27:35PM +0530, Manivannan Sadhasivam wrote: >>> On Wed, May 20, 2026 at 07:25:01PM +0300, Dmitry Baryshkov wrote: >>>> On Mon, May 18, 2026 at 10:47:16PM -0700, Qiang Yu wrote: >>>>> Some QMP PCIe PHY hardware blocks can be split into multiple sub-PHYs >>>>> under a single DT node, each requiring its own pipe clock registration and >>>>> DT resource mapping. The current helpers are tightly coupled to a single >>>>> qmp_pcie instance, which prevents reuse across sub-PHY instances. >>>>> >>>>> Refactor __phy_pipe_clk_register() as a generic helper and reduce >>>>> phy_pipe_clk_register() to a thin wrapper around it. Similarly, extract >>>>> qmp_pcie_parse_dt_common() from qmp_pcie_parse_dt() to hold the register- >>>>> mapping and pipe-clock setup that will be shared between sub-PHY instances, >>>>> with pipe clock names parameterised per instance. >>>>> >>>>> This is a preparatory step before adding multi-PHY support. No functional >>>>> change for existing platforms. >>>>> >>>>> Signed-off-by: Qiang Yu >>>>> --- >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 76 ++++++++++++++++++-------------- >>>>> 1 file changed, 44 insertions(+), 32 deletions(-) >>>> >>>> I'd suggest splitting the Glymur PHY to a separate driver. Otherwise we >>>> end up having too many single-platform, single-device specifics which >>>> don't apply to other platforms. >>>> >>> >>> I don't think that's really needed. This shared PHY concept is going to be >>> applicable to upcoming SoCs as well. And moreover, the split won't be clean >>> either. We still need to reuse a lot of common logic in the 'phy-qcom-qmp-pcie' >>> driver and may only end up keeping very minimal code in >>> 'phy-qcom-qmp-pcie-glymur'. >> >> Then splitting makes even more sense. Let's not clutter the existing >> driver with too many conditions and options. >> >>> >>> If you are concerned about the file size of 'phy-qcom-qmp-pcie', then we should >>> move the SoC specific 'cfg' structs into a separate file as that's what >>> occupying majority of the space. >> >> No, it's really the 'shared' part. >> > > To confirm, are you okay with some code duplication between the new > Glymur-specific driver and phy-qcom-qmp-pcie driver. That's a necessity, to some degree. See e.g. qmp-combo and qmp-usbc Konrad