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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c8665186aefsm12630035a12.15.2026.06.16.19.31.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jun 2026 19:31:52 -0700 (PDT) Message-ID: <1bcf00ae-2558-4c3a-970d-aee1da0c06f9@oss.qualcomm.com> Date: Wed, 17 Jun 2026 10:31:47 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] input: misc: Add Qualcomm SPMI PMIC haptics driver To: Konrad Dybcio , linux-arm-msm@vger.kernel.org, Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Stephen Boyd , Bjorn Andersson , Konrad Dybcio Cc: David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , kernel@oss.qualcomm.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260616-qcom-spmi-haptics-v1-0-d24e422de6b4@oss.qualcomm.com> <20260616-qcom-spmi-haptics-v1-3-d24e422de6b4@oss.qualcomm.com> Content-Language: en-US From: Fenglin Wu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: N06x-roifO2cwoC7vbThm7CO8EOe9vN4 X-Authority-Analysis: v=2.4 cv=IeC3n2qa c=1 sm=1 tr=0 ts=6a32071a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=-Z37uosrcRa51fMA2KUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDAyMSBTYWx0ZWRfX5uTRGp3wDW8y jeK3/e/1iZogKY9T090SiW55wr1990X91nQuSlMNvZjIqK7TIfctovkxV5Alhvvrq57iRAZrrr/ Am8riCpidRlHXt2TeQUGRMeRz03Ymp4= X-Proofpoint-ORIG-GUID: N06x-roifO2cwoC7vbThm7CO8EOe9vN4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDAyMSBTYWx0ZWRfXz+d3+IL8bW09 ld1k2iz7z+boLh25bah4axQqrQqe+YeRbUbqHhYhTd1lPge6dpP2Xjvx4rVClXB0Mpne3V/GCXT ZpURCFh0JREpyYDlhSvM2toyaysXpGuMO9YWiYyOGE20NjsKv73oEfTY8Z97OX1SmFbAt1C55Ap fKF92+nRHmaqLT8FN8N78+1KCdF3x7CrRT+3YLzHzISSUEkD7ycDyNkmBThNXSnNm3FUwsOaoze lQJP3uDfc7VkFMfEZOgjnYWgHzUJD7dCN9b6CXcIf0g7qa8+La+HnzbmowUiDqBjLsuktsqpqjV pv9QdZWbdptb+Lowa4NQg/y6FsF1fTzfJ9z8JQzHWA+HYDUfc5psAOmKEShHz1Jc41ECKz8ka3b rmz9NU7TXWZUQuQQgKDr2aUGdMqfOsViCygnZFc/NAEJsDDhj5KFEco3VQ4R3dN/U1CaQPzLdTL RPNVHBlhWF8uvArSQPQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_05,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170021 >> + ret = ptn_bulk_write(h, HAP_PTN_FIFO_DIN_0_REG, &data[i], 4); >> + if (ret) >> + return ret; >> + } >> + >> + for (; i < len; i++) { >> + ret = ptn_write(h, HAP_PTN_FIFO_DIN_1B_REG, (u8)data[i]); >> + if (ret) >> + return ret; >> + } > So if i'm reading this right, the first loop will always write > 4*(len//4) bytes and the second one will be entered at most once, > to write len rem 4 bytes.. should this be an if instead? I should put a comment for clarification. Here’s some background: FIFO data writing supports both 4-byte bulk writes using registers [HAP_PTN_FIFO_DIN_0_REG ... HAP_PTN_FIFO_DIN_3_REG], and 1-byte writes using the HAP_PTN_FIFO_DIN_1B_REG register. The 4-byte bulk write is more efficient, especially for waveform which has several Kb data, and it helps to reduce software latency when loading effects and reduce the delay in triggering vibration. It also helps prevent the FIFO from running dry during data refill in FIFO-empty interrupts. Typically, we use 4-byte writes for the initial 4-byte aligned data, and 1-byte writes for any trailing remainder. So it still needs a 'for' loop here since the remainder could be more than 1 byte. >> + >> + return 0; >> +} >> + >> +/* >> + * Configure the hardware FIFO memory boundary. >> + * FIFO occupies addresses [0, fifo_len). >> + */ >> +static int haptics_configure_fifo_mmap(struct qcom_haptics *h) >> +{ >> + u32 fifo_len, fifo_units; >> + >> + /* Config all memory space for FIFO usage for now */ > What's the not-"for now" endgame for this? The hardware supports more modes than the two currently supported in the driver. One of these, called 'PAT_MEM' mode, also shares memory space with FIFO mode. However, 'PAT_MEM' requires memory to be pre-reserved and waveform data to be pre-loaded. The entire 8K bytes of memory can be divided into partitions, and it is configurable, with FIFO mode always using the first partition [0, fifo_len], where 'fifo_len' is set via the 'MMAP_FIFO_REG' register. 'PAT_MEM' mode plays waveform using data preloaded in a memory bank defined by the registers 'PATX_MEM_START_ADDR_REG' and 'PATTERN_SPMI_PATX_LEN_REG' (they are not defined in the driver). Since PAT_MEM is mainly intended for hardware-triggered vibrations, such as a signal from a dedicated GPIO triggering a short vibration with a preloaded waveform, and although it also supports software triggers, I haven't found a suitable way to support it well into the driver under input FF framework yet. So, I am currently allocating the entire 8K FIFO memory for FIFO mode only. We can adjust this later if we find a better way to incorporate 'PAT_MEM' mode into the driver.