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From: Stephen Boyd <sboyd@kernel.org>
To: "Michael Turquette" <mturquette@baylibre.com>,
	"Théo Lebrun" <theo.lebrun@bootlin.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-mips@vger.kernel.org,
	"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
	"Grégory Clement" <gregory.clement@bootlin.com>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
	"Théo Lebrun" <theo.lebrun@bootlin.com>
Subject: Re: [PATCH v6] clk: eyeq: add driver
Date: Mon, 28 Oct 2024 16:38:00 -0700	[thread overview]
Message-ID: <1be883e74445353163ed94f273aa4a0d.sboyd@kernel.org> (raw)
In-Reply-To: <20241023-mbly-clk-v6-1-ca83e43daf93@bootlin.com>

Quoting Théo Lebrun (2024-10-23 03:58:40)
> Add Mobileye EyeQ5, EyeQ6L and EyeQ6H clock controller driver. It is
> both a platform driver and a hook onto of_clk_init() used for clocks
> required early (GIC timer, UARTs).
> 
> For some compatible, it is both at the same time. eqc_early_init()
> initialises early PLLs and exposes its own clock provider. It marks
> other clocks as deferred. eqc_probe() adds all remaining clocks using
> another clock provider.
> 
> It exposes read-only PLLs derived from the main crystal on board.
> It also exposes another type of clocks: divider clocks.
> They always have even divisors and have one PLL as parent.
> 
> This driver also bears the responsability for optional reset and pinctrl
> auxiliary devices. The match data attached to the devicetree node
> compatible indicate if such devices should be created. They all get
> passed a pointer to the start of the OLB region.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---

Applied to clk-next

      reply	other threads:[~2024-10-28 23:38 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-23 10:58 Théo Lebrun
2024-10-28 23:38 ` Stephen Boyd [this message]

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