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If it turns out that BIOS has enabled the feature for > years on a wide range of Endpoints without any issues, I think > that would render concerns mute that enabling it in the kernel > might cause regressions. > > I don't know why the spec says that "discovery of AtomicOp Requester > capabilities is outside the scope of this specification". I imagine > it would be possible to set AtomicOp Requester Enable, then read it > to determine whether the bit is now indeed 1 or hard-wired to 0. > In the latter case, AtomicOp Requester capabilities can be assumed > to be absent. So that would be a way to make do without any other > specific discovery of AtomicOp Requester capabilities. Sorry for getting back to this very late. The approach taken by our Platform FW is not as robust as how it is handled by SW. And also they haven't come across issues for AtomicOps similar to 10-bit tags. Hence, I worked on the approach of reading back the "AtomicOp Requester Enable" to determine whether it is indeed 1 or hard-wired to 0. I came across two issues. This approach did not eliminate calling pci_enable_atomic_ops_to_root() on all drivers as some of them enabled AtomicOp by only checking for 32-bit and 64-bit Completion capabilities. And, on internal review I received comments that this approach wouldn't help in determining the presence/absence of AtomicOps. PCIe r6.0 sec 7.5.3.16 [1], states "AtomicOps Requester Enable is permitted to be RW even if no AtomicOp Requester capabilities are supported by the Endpoint or Root Port", thereby substantiating devices that hardwires this bit to '1' is also valid.. I have sent v4 considering all these constraints. Let me know what you think. Thanks, Smita > > Thanks, > > Lukas