From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 292973FBB3; Mon, 15 Sep 2025 07:13:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920430; cv=none; b=S+kp2uJ+nuuOtwMPZvQW5dwJrgf+4ChJiGznVisRlIgw5eGUS2bkJcO/xw0KYMyJQOr3x7H2xBdgRo1e6GoRsSfLlvQo33LE9RdBdtQ8fTaTvoB05YJRwMYjCQjHOGYfP6x9dPWAmT4kGuN7B9RzNOzFGyLRJNLZEytX1uU51Jg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920430; c=relaxed/simple; bh=RBstruI8aqugkuKemrcCOfrfs1zaZlQtORPCGRJvYzc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=kjnt4r5qD4VDmNwevo5T+2n117iE+aSzai9OMYQMLMIGv4yc+c7Mpg5Z/6HJncE5TiJhiMJ0K9fw4x2gSXSH7T1v4mdHI5dJirybaFfHcU7eqjl1Rj+JNrzJjALyI4ApR7EK5QIBZKONh4wmtYAEEa0t1413K1Bkha6dnHgPyrM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c/Y1rC2R; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c/Y1rC2R" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97EF1C4CEF1; Mon, 15 Sep 2025 07:13:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757920429; bh=RBstruI8aqugkuKemrcCOfrfs1zaZlQtORPCGRJvYzc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=c/Y1rC2RXw5SHanCMfXuzcRpXdyyZbTe3o+eCac2xnhgaJJhUHQahwsK4bjh6uurl xFwWBUJE5QxdUV/Y57+UZVXbOmaaaQcEUJvpgI9s8VzbGMhKrUSAPNcxvBCYq28Xrh wMzYcKrdQZ3HmVEtydAqCFL2v/pQ0q1l/4lSEtS3n+KxJXyEK0zsl9S+4vRpVHudEa mR+gT+ljkgnoHnoXnm6jq2NzZtAbJq0elpa5HeMOacW2JbJdMQk1y7gV+kB72yeHA7 CQRs0e3Kvw9+NfjW7kfeJ7zcdBRgTKb4oXmN93oGtUnKRcOq5NqO4kOClDq1yaXP09 9FLOT3xeB0Oqg== Message-ID: <1c16121a-36a6-4101-9a2c-d45547c6ea0a@kernel.org> Date: Mon, 15 Sep 2025 09:13:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] iommu/exynos: Implement register set and fault handling on SysMMU v9 To: "myunggeun.ji" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Marek Szyprowski , Joerg Roedel , Will Deacon , Robin Murphy , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev Cc: Jongho Park , kiisung lee References: <20250915051320.3378957-1-myunggeun.ji@samsung.com> <20250915051320.3378957-2-myunggeun.ji@samsung.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 15/09/2025 07:13, myunggeun.ji wrote: > + > static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) > { > return container_of(dom, struct exynos_iommu_domain, domain); > @@ -522,19 +571,26 @@ static void __sysmmu_get_version(struct sysmmu_drvdata *data) > ver = readl(data->sfrbase + REG_MMU_VERSION); > > /* controllers on some SoCs don't report proper version */ > + Please clean up your patch before posting. > if (ver == 0x80000001u) > data->version = MAKE_MMU_VER(1, 0); > else > data->version = MMU_RAW_VER(ver); > > - dev_dbg(data->sysmmu, "hardware version: %d.%d\n", > - MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); > + if (data->version != 0x91) > + dev_err(data->sysmmu, "hardware version: %d.%d\n", > + MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); > + else if (data->version == 0x91) > + dev_err(data->sysmmu, "hardware version: %d.%d\n", > + MMU_MAJ_VER_V9(data->version), MMU_MIN_VER_V9(data->version)); > > - if (MMU_MAJ_VER(data->version) < 5) { > + if (data->version == 0x91) { > + data->variant = &sysmmu_v9_vm_variant; > + } else if (MMU_MAJ_VER(data->version) < 5) { > data->variant = &sysmmu_v1_variant; > } else if (MMU_MAJ_VER(data->version) < 7) { > data->variant = &sysmmu_v5_variant; > - } else { > + } else if (MMU_MAJ_VER(data->version) < 9) { > if (__sysmmu_has_capa1(data)) > __sysmmu_get_vcr(data); > if (data->has_vcr) > @@ -763,10 +819,9 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) > if (IS_ERR(data->pclk)) > return PTR_ERR(data->pclk); > > - if (!data->clk && (!data->aclk || !data->pclk)) { > - dev_err(dev, "Failed to get device clock(s)!\n"); > - return -ENOSYS; > - } > + /* There is no clock information after v9 */ There is, you just missed to implement it. > + if (!data->clk && (!data->aclk || !data->pclk)) > + dev_warn(dev, "Failed to get device clock(s)!\n"); > Best regards, Krzysztof