From: Jon Hunter <jonathanh@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 2/3] clk: tegra: Add more rates to Tegra30 PLLX frequency table
Date: Wed, 17 Oct 2018 09:59:02 +0100 [thread overview]
Message-ID: <1c4e20b2-9929-b163-b371-b32596b6189a@nvidia.com> (raw)
In-Reply-To: <20180830192045.11017-3-digetx@gmail.com>
On 30/08/2018 20:20, Dmitry Osipenko wrote:
> Add more predefined rates to the PLLX table, allowing to lower the rate
> down to 312MHz. This gives more variations of frequency selection to the
> CPUFREQ driver.
If these tables are pulled from some other NVIDIA kernel or a particular
document, I always like to see a reference to where these came from so
we can always refer back to them.
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2018-10-17 8:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-30 19:20 [PATCH v1 0/3] CPU clock changes for Tegra20/30 Dmitry Osipenko
2018-08-30 19:20 ` [PATCH v1 1/3] clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30 Dmitry Osipenko
2018-10-17 8:53 ` Jon Hunter
2018-10-17 12:27 ` Dmitry Osipenko
2018-08-30 19:20 ` [PATCH v1 2/3] clk: tegra: Add more rates to Tegra30 PLLX frequency table Dmitry Osipenko
2018-10-17 8:59 ` Jon Hunter [this message]
2018-10-17 12:14 ` Dmitry Osipenko
2018-08-30 19:20 ` [PATCH v1 3/3] clk: tegra: Poll PLLX lock-status on resume from suspend on Tegra20/30 Dmitry Osipenko
2018-10-16 22:29 ` [PATCH v1 0/3] CPU clock changes for Tegra20/30 Stephen Boyd
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