From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423351AbcFNA25 (ORCPT ); Mon, 13 Jun 2016 20:28:57 -0400 Received: from lucky1.263xmail.com ([211.157.147.133]:56625 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423167AbcFNA24 (ORCPT ); Mon, 13 Jun 2016 20:28:56 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: linux-arm-kernel@lists.infradead.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <744a33a42f89e37f2e5c84bd41136829> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 01/11] phy: rockchip-emmc: Increase lock time allowance To: Douglas Anderson , ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org References: <1465859076-4868-1-git-send-email-dianders@chromium.org> <1465859076-4868-2-git-send-email-dianders@chromium.org> Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Shawn Lin Message-ID: <1c62147b-0464-6ecc-3ba4-2ec9ddf19111@rock-chips.com> Date: Tue, 14 Jun 2016 08:28:46 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <1465859076-4868-2-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ÔÚ 2016/6/14 7:04, Douglas Anderson дµÀ: > Previous PHY code waited a fixed amount of time for the DLL to lock at > power on time. Unfortunately, the time for the DLL to lock is actually > a bit more dynamic and can be longer if the card clock is slower. > > Instead of waiting a fixed 30 us, let's now dynamically wait until the > lock bit gets set. We'll wait up to 10 ms which should be OK even if > the card clock is at the super slow 100 kHz. > > On its own, this change makes the PHY power on code a little more > robust. Before this change the PHY was relying on the eMMC code to make > sure the PHY was only powered on when the card clock was set to at least > 50 MHz before, though this reliance wasn't documented anywhere. > > This change will be even more useful in future changes where we actually > need to be able to wait for a DLL lock at slower clock speeds. > Looks good to me. Reviewed-by: Shawn Lin > Signed-off-by: Douglas Anderson > --- > Changes in v2: > - Indicate that 5.1 ms is calculated (Shawn). > > drivers/phy/phy-rockchip-emmc.c | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c > index a69f53630e67..2d059c046978 100644 > --- a/drivers/phy/phy-rockchip-emmc.c > +++ b/drivers/phy/phy-rockchip-emmc.c > @@ -85,6 +85,7 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, > { > unsigned int caldone; > unsigned int dllrdy; > + unsigned long timeout; > > /* > * Keep phyctrl_pdb and phyctrl_endll low to allow > @@ -137,15 +138,26 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, > PHYCTRL_ENDLL_MASK, > PHYCTRL_ENDLL_SHIFT)); > /* > - * After enable analog DLL circuits, we need an extra 10.2us > - * for dll to be ready for work. But according to testing, we > - * find some chips need more than 25us. > + * After enabling analog DLL circuits docs say that we need 10.2 us if > + * our source clock is at 50 MHz and that lock time scales linearly > + * with clock speed. If we are powering on the PHY and the card clock > + * is super slow (like 100 kHZ) this could take as long as 5.1 ms as > + * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms > + * Hopefully we won't be running at 100 kHz, but we should still make > + * sure we wait long enough. > */ > - udelay(30); > - regmap_read(rk_phy->reg_base, > - rk_phy->reg_offset + GRF_EMMCPHY_STATUS, > - &dllrdy); > - dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; > + timeout = jiffies + msecs_to_jiffies(10); > + do { > + udelay(1); > + > + regmap_read(rk_phy->reg_base, > + rk_phy->reg_offset + GRF_EMMCPHY_STATUS, > + &dllrdy); > + dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; > + if (dllrdy == PHYCTRL_DLLRDY_DONE) > + break; > + } while (!time_after(jiffies, timeout)); > + > if (dllrdy != PHYCTRL_DLLRDY_DONE) { > pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); > return -ETIMEDOUT; > -- Best Regards Shawn Lin