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From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Potin Lai <potin.lai.pt@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Patrick Williams <patrick@stwcx.xyz>,
	 devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
	Potin Lai <potin.lai@quantatw.com>,
	Cosmo Chou <cosmo.chou@quantatw.com>
Subject: Re: [PATCH 1/2] ARM: dts: aspeed: catalina: update pdb board cpld ioexp linename
Date: Fri, 08 Nov 2024 10:07:31 +1030	[thread overview]
Message-ID: <1c8f39015eae7cc71fbfb9136af8a728d743a991.camel@codeconstruct.com.au> (raw)
In-Reply-To: <CAGfYmwVxwaZk-si1OkP4xeaODhAO74Hv43U=SpzOsGOBkTH8Bw@mail.gmail.com>

On Thu, 2024-11-07 at 19:22 +0800, Potin Lai wrote:
> On Thu, Nov 7, 2024 at 7:41 AM Andrew Jeffery
> <andrew@codeconstruct.com.au> wrote:
> > 
> > On Wed, 2024-11-06 at 16:58 +0800, Potin Lai wrote:
> > > Update the GPIO linename of each PDB CPLD IO expander based on
> > > latest
> > > CPLD firmware.
> > 
> > What version is the latest CPLD firmware? What was the previous
> > version
> > with the old pin assignments?
> 
> Because the hardware changes from EVT to DVT, the CPLD firmware
> reallocated the IOEXP pin mapping in DVT version.
> I will add more description into the commit message in the next
> version.

If you have different revisions of the board, it would seem sensible to
have separate devicetrees, one for each, rather than constantly
evolving one devicetree? Tack on an `-evt`/`-dvt` suffix as required?
From there you can always have a suffix-less dts file that #includes
the most recent board revision. See some of the Aspeed EVB devicetrees
for an example.

> 
> > 
> > I'm also interested in some discussion of the coordination between
> > CPLD
> > firmware, the devicetree and the BMC userspace configuration. This
> > change feels pretty painful.
> 
> I am not from the CPLD firmware team,

I don't see why you need to be? This is a cross-component concern, and
you need to make all the pieces of the puzzle line up.

>  I only know our CPLD team was
> redesigning the entire struct which causes the huge changes of IOEXP
> pins.
> 
> This is probably a different topic, I am curious about is it possible
> to assign the linename in userspace?
> In OpenBMC, there are many services that depend on GPIO linename, it
> will be more flexible if I can assign the linename before service
> starts.

Not that I'm aware, and to determine otherwise I'd probably need to
read the implementation as much as you :)

However, separating the devicetrees would go a long way here if the
CPLD firmware is tied to the board revision...

Andrew

  reply	other threads:[~2024-11-07 23:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-06  8:58 [PATCH 0/2] ARM: dts: aspeed: catalina: update CPLD IO expander pin definitions Potin Lai
2024-11-06  8:58 ` [PATCH 1/2] ARM: dts: aspeed: catalina: update pdb board cpld ioexp linename Potin Lai
2024-11-06 23:41   ` Andrew Jeffery
2024-11-07 11:22     ` Potin Lai
2024-11-07 23:37       ` Andrew Jeffery [this message]
2024-11-06  8:58 ` [PATCH 2/2] ARM: dts: aspeed: catalina: add hdd board cpld ioexp Potin Lai
2024-11-06 23:42   ` Andrew Jeffery

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