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So the linear >> mapping is determined by the capability of boot CPU only. If the boot >> CPU supports BBML2, large block mappings will be used for linear >> mapping. >> >> But the secondary CPUs may not support BBML2, so repaint the linear >> mapping if large block mapping is used and the secondary CPUs don't >> support BBML2 once cpufeature is finalized on all CPUs. >> >> If the boot CPU doesn't support BBML2 or the secondary CPUs have the >> same BBML2 capability with the boot CPU, repainting the linear mapping >> is not needed. >> >> Repainting is implemented by the boot CPU, which we know supports BBML2, >> so it is safe for the live mapping size to change for this CPU. The >> linear map region is walked using the pagewalk API and any discovered >> large leaf mappings are split to pte mappings using the existing helper >> functions. Since the repainting is performed inside of a stop_machine(), >> we must use GFP_ATOMIC to allocate the extra intermediate pgtables. But >> since we are still early in boot, it is expected that there is plenty of >> memory available so we will never need to sleep for reclaim, and so >> GFP_ATOMIC is acceptable here. >> >> The secondary CPUs are all put into a waiting area with the idmap in >> TTBR0 and reserved map in TTBR1 while this is performed since they >> cannot be allowed to observe any size changes on the live mappings. Some >> of this infrastructure is reused from the kpti case. Specifically we >> share the same flag (was __idmap_kpti_flag, now idmap_kpti_bbml2_flag) >> since it means we don't have to reserve any extra pgtable memory to >> idmap the extra flag. >> >> Co-developed-by: Yang Shi >> Signed-off-by: Yang Shi >> Signed-off-by: Ryan Roberts > I think this works, so: > > Reviewed-by: Catalin Marinas Thank you! > > However, I wonder how likely we are to find this combination in the > field to be worth carrying this code upstream. With kpti, we were aware > of platforms requiring it but is this also the case for BBM? If not, I'd > keep the patch out until we get a concrete example. At least we (Ampere) are very very unlikely to ship asymmetric systems AFAICT. Thanks, Yang >