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Fri, 04 Apr 2025 14:29:07 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A2B994005F; Fri, 4 Apr 2025 14:28:07 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E97BE9234AC; Fri, 4 Apr 2025 14:27:32 +0200 (CEST) Received: from [10.130.77.120] (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 4 Apr 2025 14:27:32 +0200 Message-ID: <1c9a49cb-35a1-4bcc-abd5-b14a49d4d094@foss.st.com> Date: Fri, 4 Apr 2025 14:17:08 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: st: add st,stm32mp2-cortex-a7-gic in intc node in stm32mp251.dtsi To: Marc Zyngier CC: , , , , , , , , , References: <20250403122805.1574086-1-christian.bruel@foss.st.com> <20250403122805.1574086-4-christian.bruel@foss.st.com> <874iz5yx2c.wl-maz@kernel.org> From: Christian Bruel Content-Language: en-US In-Reply-To: <874iz5yx2c.wl-maz@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-04_05,2025-04-03_03,2024-11-22_01 On 4/3/25 19:27, Marc Zyngier wrote: > On Thu, 03 Apr 2025 13:28:05 +0100, > Christian Bruel wrote: >> >> Add st,stm32mp2-cortex-a7-gic to enable the GICC_DIR register remap >> >> Signed-off-by: Christian Bruel >> --- >> arch/arm64/boot/dts/st/stm32mp251.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi >> index f3c6cdfd7008..030e5da67a7e 100644 >> --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi >> +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi >> @@ -115,7 +115,7 @@ scmi_vdda18adc: regulator@7 { >> }; >> >> intc: interrupt-controller@4ac00000 { >> - compatible = "arm,cortex-a7-gic"; >> + compatible = "st,stm32mp2-cortex-a7-gic", "arm,cortex-a7-gic"; > > What nonsense is this? This is an *arm64* machine, with I expect a > GIC400. Where is this A7 compat coming from? Probably historical, as the first port was for aarch32. I will fix this separately. thanks for the head up! Christian > > M. >