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From: "Liang, Kan" <kan.liang@linux.intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
	namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com,
	jolsa@kernel.org, alexander.shishkin@linux.intel.com,
	linux-kernel@vger.kernel.org, dapeng1.mi@linux.intel.com,
	ak@linux.intel.com, zide.chen@intel.com, mark.rutland@arm.com,
	broonie@kernel.org, ravi.bangoria@amd.com
Subject: Re: [RFC PATCH V2 03/13] x86/fpu/xstate: Add xsaves_nmi
Date: Mon, 7 Jul 2025 11:12:03 -0700	[thread overview]
Message-ID: <1cb07a5b-fc14-481f-b145-56803edeb0d0@linux.intel.com> (raw)
In-Reply-To: <3e95a8f7-88aa-4732-b38b-ccef74634819@intel.com>



On 2025-07-01 5:18 p.m., Chang S. Bae wrote:
> On 6/26/2025 12:56 PM, kan.liang@linux.intel.com wrote:
> <snip>> Add an interface to retrieve the actual register contents when
> the NMI
>> hit. The interface is different from the other interfaces of FPU. The
>> other mechanisms that deal with xstate try to get something coherent.
>> But this interface is *in*coherent. There's no telling what was in the
>> registers when a NMI hits. It writes whatever was in the registers when
>> the NMI hit. It's the invoker's responsibility to make sure the contents
>> are properly filtered before exposing them to the end user.
> 
> <snip>
> 
>>   +/**
>> + * xsaves_nmi - Save selected components to a kernel xstate buffer in
>> NMI
>> + * @xstate:    Pointer to the buffer
>> + * @mask:    Feature mask to select the components to save
>> + *
>> + * The @xstate buffer must be 64 byte aligned.
>> + *
>> + * Caution: The interface is different from the other interfaces of FPU.
>> + * The other mechanisms that deal with xstate try to get something
>> coherent.
>> + * But this interface is *in*coherent. There's no telling what was in
>> the
>> + * registers when a NMI hits. It writes whatever was in the registers
>> when
>> + * the NMI hit.
>> + * The only user for the interface is perf_event. There is already a
>> + * hardware feature (See Intel PEBS XMMs group), which can handle XSAVE
>> + * "snapshots" from random code running. This just provides another
>> XSAVE
>> + * data source at a random time.
>> + * This function can only be invoked in an NMI. It returns the *ACTUAL*
>> + * register contents when the NMI hit.
>> + */
>> +void xsaves_nmi(struct xregs_state *xstate, u64 mask)
>> +{
>> +    int err;
>> +
>> +    if (!in_nmi())
>> +        return;
>> +
>> +    XSTATE_OP(XSAVES, xstate, (u32)mask, (u32)(mask >> 32), err);
>> +    WARN_ON_ONCE(err);
>> +}
>> +
> There are xsaves()/xrstors() functions, already narrowed to the
> "independent" feature set only. So, adding a new xsaves_yyy() variant
> for a different use case -- without renaming the existing helpers to
> something like xsaves_xxx() -- would make the naming scheme appear
> inconsistent at a glance.
> 
> But looking back at history:
> 
> 1. These helpers were established with "independent" in the name (though
>    they were initially described as for “dynamic” features):
>    copy_kernel_to_independent_supervisor()/
>    copy_independent_supervisor_to_kernel()
> 
> 2. Later, Thomas reworked them, renaming and simplifying them to
>    xsaves()/xrstors(), and adding a refactored validator:
>    validate_xsaves_xrstors() [1]. At that point, their usage was
>    *relaxed* and not strictly limited to independent features.
> 
> 3. Subsequently, in preparation for dynamic feature support, the helpers
>    were restricted again to independent features only [2]. This involved
>    renaming and enforcing stricter validation via
>    validate_independent_components().
> 
> Given that, rather than introducing a new wrapper for every additional
> use case, another option could be to retain xsaves() naming but modestly
> expand its scope. That would mean to add another allowance: features in
> tightly constrained contexts (e.g., NMI). Perhaps, this approach can
> keep the API simple while still expanding usage.
>

So we need to add a parameter, e.g., nmi. For the NMI case, the limit to
the independent features should be removed, right?
void xsaves(struct xregs_state *xsave, u64 mask, bool nmi);

The only user for the xsaves is LBR. It should not be a problem to
update the interface.
But perf only needs the xsaves for the SIMD and other registers. So the
parameter will only be added for the xsaves(). The xsaves()/xrstore()
will not be symmetrical anymore. I'm not sure if it's a problem.

Dave? Thomas? Any comments?

Should we extend the existing xsaves() interface or adding a new
xsaves_nmi() interface for the perf usage?

Thanks,
Kan


> [1] a75c52896b6d ("x86/fpu/xstate: Sanitize handling of independent
> features")
> [2] f5daf836f292 ("x86/fpu: Restrict xsaves()/xrstors() to independent
> states")
> 
> 


  reply	other threads:[~2025-07-07 18:12 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-26 19:55 [RFC PATCH V2 00/13] Support vector and more extended registers in perf kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 01/13] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 02/13] perf/x86: Setup the regs data kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 03/13] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-07-02  0:18   ` Chang S. Bae
2025-07-07 18:12     ` Liang, Kan [this message]
2025-07-07 18:17       ` Dave Hansen
2025-06-26 19:56 ` [RFC PATCH V2 04/13] perf: Move has_extended_regs() to header file kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 05/13] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-27 14:35   ` Dave Hansen
2025-06-27 21:23     ` Liang, Kan
2025-06-26 19:56 ` [RFC PATCH V2 06/13] perf: Support SIMD registers kan.liang
2025-07-02 11:16   ` Mark Brown
2025-07-07 18:12     ` Liang, Kan
2025-06-26 19:56 ` [RFC PATCH V2 07/13] perf/x86: Move XMM to sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 08/13] perf/x86: Add YMM into sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 09/13] perf/x86: Add ZMM " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 10/13] perf/x86: Add OPMASK into sample_simd_pred_reg kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 11/13] perf/x86: Add eGPRs into sample_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 12/13] perf/x86: Add SSP " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 13/13] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS kan.liang

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