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charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=VKVIDNPX c=1 sm=1 tr=0 ts=6aad7d85 cx=c_pps a=gjcLB77VbSPYcqvaeYBpgA==:117 a=f+v6EHfkeJbVwR46tk4DMg==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=TXF05nYbSb0vizRg:21 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s63m1ICgrNkA:10 a=V5UXEbMT0ywA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z8NIEmU8O1QQgoT56wFK:22 a=jwouBfj2j3NM8CExmVVE:22 a=RpNjiQI2AAAA:8 a=sozttTNsAAAA:8 a=uherdBYGAAAA:8 a=gEfo2CItAAAA:8 a=NEAV23lmAAAA:8 a=hqgTioDd-K5usMiy-fsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDI2MCBTYWx0ZWRfX+/9A+AXIT8CL f4luO2O78zoVvck729uJp5rPUeim643U2/kkGG/y/CIZzp4o6ek9A9qKMbNONoMxyF35jtwDzkx cvOv7tb/6guGkAwg5nkAoWCJY8F/o3EvUepSYFs+9wERcSvxtUJr9pGSs9h4I/tHglzlV23ylTU GsLSSDm4wY75kM4raeeZxC4p535Kp9VrvMjNkf+FAODFSeDbJTXxag5r503MDDcdDMMyzr41zmW xvmW4c4P5glC3Pj4UrQYtA3Gu4XeHp+KV/jJa07I49GjHn19snhHMwHkzg+jJ1aPlv0Al6BPsbq oytnANQWhi7r29uPAP2fkW+zeKx5Uc9CBiBcFrgwkuUymiJLucr3zHQ5i4tSgQnhMs7nkjBBKGw nRF0vOPHWQwfQ0y6nS+6uLLC8h9+gEu92H0UOPBuoXJfELHZn7yifVMFMzE2OiGYN4U8KcJ2Bxc P/Ow4ujycnQrbpPlNbw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDI2MCBTYWx0ZWRfXxYrbkbihfqGq fuPq5y/BStO+jNTjVT7ZEWbxUV2LyuypOf6gplfRj7tmi7N1gh4jRSGqbmZtSYt19jkp0aBj+fs MjKpmNhzhv8T9fGaumZJmcSPwHaiOUQ= X-Proofpoint-GUID: K5CBEF5PSARXm9bsu1KqdaCrSh2luXfM X-Proofpoint-ORIG-GUID: K5CBEF5PSARXm9bsu1KqdaCrSh2luXfM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-18_05,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1011 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180260 Hi Conor, On 18/09/26 03:40, Conor wrote: > On 17 September 2026 17:=E2=80=8A44:=E2=80=8A21 GMT+02:=E2=80=8A00, rahul= sharma > wrote: >Hi Conor, > >On 15/09/26 19:=E2=80=8A19, Conor Dooley wrote: >> O= n Tue, Sep 15, > 2026 at 06:=E2=80=8A10:=E2=80=8A45PM +0530, rahul sharma wrote: >>> Hi Co= nor, >=20 >=20 >=20 > On 17 September 2026 17:44:21 GMT+02:00, rahul sharma = wrote: >>Hi Conor, >> >>On 15/09/26 19:19, Conor Dooley wrote: >>> On Tue, Sep 15, 2026 at 06:10:45PM +0530, rahul sharma wrote: >>>> Hi Conor, >>>>=20 >>>> Thanks for reviewing. >>>> Apologies for the delay in responding. >>>>=20 >>>> On 28/08/26 21:57, Conor Dooley wrote: >>>>> On Fri, Aug 28, 2026 at 03:36:14PM +0530, Rahul Sharma wrote: >>>>>> Add binding for the event mux router of TI's K3 based SoC AM62L. >>>>>>=20 >>>>>> The TI K3 mux routers which route the GPIO input events or Time-Sync >>>>>> events b/w peripherals instead of routing to a CPU. >>>>>>=20 >>>>>> Refer Section 10.2 and 10.2.1 of https://www.ti.com/lit/pdf/sprujb4= =20 >>>>>>=20 >>>>>> Signed-off-by: Rahul Sharma >>>>>> --- >>>>>> .../mux/ti,am62l-event-mux-router.yaml | 79 ++++++++++++++= +++++ >>>>>> 1 file changed, 79 insertions(+) >>>>>> create mode 100644 Documentation/devicetree/bindings/mux/ti,am62l= -event-mux-router.yaml >>>>>>=20 >>>>>> diff --git a/Documentation/devicetree/bindings/mux/ti,am62l-event-mu= x-router.yaml b/Documentation/devicetree/bindings/mux/ti,am62l-event-mux-ro= uter.yaml >>>>>> new file mode 100644 >>>>>> index 000000000000..a5ba7f78a156 >>>>>> --- /dev/null >>>>>> +++ b/Documentation/devicetree/bindings/mux/ti,am62l-event-mux-route= r.yaml >>>>>> @@ -0,0 +1,79 @@ >>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>>> +%YAML 1.2 >>>>>> +--- >>>>>> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/mux/= ti,am62l-event-=20 > mux-router.yaml*__;Iw!!G3vK!VJUh5A8cDCko1ZAGtTQ8V- > LL1vTj1BNr5NNBonzfy5GnFCQkP4Oc-0Kkq4xVdCcEA5bQcDckFu6UyA$ >>>>>> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-sch= emas/core.yaml*__;Iw!!=20 > G3vK!VJUh5A8cDCko1ZAGtTQ8V-LL1vTj1BNr5NNBonzfy5GnFCQkP4Oc-0Kkq4xVdCcEA5bQ= cDdyRJuLcg$ >>>>>> + >>>>>> +title: TI Event Multiplexer on K3 SoCs >>>>>> + >>>>>> +maintainers: >>>>>> + - Rahul Sharma >>>>>> + >>>>>> +description: >>>>>> + The TI K3 mux routers routes the GPIO input events or Time >>>>>> + Sync events between peripherals instead of routing to a CPU. >>>>>> + >>>>>> +allOf: >>>>>> + - $ref: mux-controller.yaml# >>>>>> + >>>>>> +properties: >>>>>> + compatible: >>>>>> + const: ti,am62l-event-mux-router >>>>>> + >>>>>> + reg: >>>>>> + description: Register base address and size. >>>>>> + maxItems: 1 >>>>>> + >>>>>> + '#mux-control-cells': >>>>>> + const: 1 >>>>>> + description: >>>>>> + Number of cells in a mux control specifier. This should be 1. >>>>>> + The cell specifies which mux control to use (0-based index). >>>>>> + >>>>>> + ti,reg-mask-val: >>>>>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >>>>>> + items: >>>>>> + items: >>>>>> + - description: Register offset (relative to reg base) >>>>>> + - description: Bit mask for the mux control bits >>>>>> + - description: Value to write when mux is active (state 1) >>>>>> + minItems: 1 >>>>>> + description: | >>>>>> + Array of triplets specifying register offset, mask, and value= for each >>>>>> + mux control. Each triplet contains: >>>>>> + - register offset (relative to reg base) >>>>>> + - bit mask for the mux control bits >>>>>> + - value to write when mux is active (state 1) >>>>>=20 >>>>> You have a device-specific compatible, why do you need this? If the >>>>> active setting depends on the device or w/e, why can that not come fr= om >>>>> a mux-control-cell? >>>>=20 >>>> This is a boot-time/board-fixed routing decision, not a runtime-select= able >>>> mux that any driver ever calls mux_control_select() on. >>>=20 >>> 2/3 of this property appears to describe the register layout of the >>> device, that's not affected by the board or some boot time decision. >>>=20 >> >>You are right about the mask element; I will move the mask into the drive= r since it is constant across all entries. However, the reg-offset must rem= ain in the DT, as it is specific to each BCDMA channel's trigger line confi= guration. This allows the DT to define the unique routing offsets required = for the hardware. >=20 > The reason you cite here for needing reg offset is exactly what using mux= -controls from a consumer node provides. I will refactor this to use mux-control-cells. I will drop=20 ti,reg-mask-val from the bindings and instead source the reg-offset and=20 value from the consumer node. BR, Rahul >=20 >> >>>>=20 >>>> Please refer below link for the IP block diagram: >>>> https://urldefense.com/v3/__https://github.com/lucifer-9852/linux/comm= it/=20 > aed1746e411a9f0ad7824f4e4a7121e6f56a4ef2__;!!G3vK!VJUh5A8cDCko1ZAGtTQ8V- > LL1vTj1BNr5NNBonzfy5GnFCQkP4Oc-0Kkq4xVdCcEA5bQcDdDoeFS5w$ >>>>=20 >>>> For detailed view of IP you can refer Section 10.2 and 10.2.1 of TRM >>>> https://www.ti.com/lit/pdf/sprujb4=20 >>>>=20 >>>> That's precisely why we added ti,reg-mask-val as a controller-side pro= perty >>>> rather than sourcing the value from a consumer's mux-control-cell: the= re is >>>> no runtime consumer selecting between states, so the routing has to be= fully >>>> described on the provider. >>>=20 >>> Why do you have #mux-control-cells if there are no consumers? I don't >>> understand why the GPIO controller or the device that the interrupt is >>> being routed to cannot have a mux-controls property that contains the >>> "value to write when the mux is active". >>>=20 >> >>You are correct regarding #mux-control-cells. Since, this driver is used = for static routing rather than runtime selection by a consumer, that proper= ty is unnecessary. I will remove it. >=20 > I still don't understand this argument, if you have a static configuratio= n just do it the probe of the consumers driver. > Then you get to use standard properties rather than encode the register m= ap in the binding... >=20 >> >>BR, >>Rahul >> >>> Confused, >>> Conor. >>>=20 >>>>=20 >>>> BR, >>>> Rahul >>>>=20 >>>>>=20 >>>>>> + >>>>>> + idle-states: >>>>>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>>>>=20 >>>>> This is not needed, you get the type from mux-controller.yaml. >>>>>=20 >>>>> pw-bot: changes-requested >>>>>=20 >>>>> Thanks, >>>>> Conor. >>>>>=20 >>>>>> + description: | >>>>>> + Idle state for each mux control. Each entry corresponds to a = mux control: >>>>>> + - 0: clear masked bits when idle, also refers to inactive sta= te >>>>>> + - 1: set configured value when idle, also refers to active st= ate >>>>>> + - MUX_IDLE_AS_IS (-1): keep current state when idle >>>>>> + >>>>>> +required: >>>>>> + - compatible >>>>>> + - reg >>>>>> + - '#mux-control-cells' >>>>>> + - ti,reg-mask-val >>>>>> + - idle-states >>>>>> + >>>>>> +additionalProperties: false >>>>>> + >>>>>> +examples: >>>>>> + - | >>>>>> + #include >>>>>> + >>>>>> + // Example 1: TI AM62L GPIO Mux Router >>>>>> + mux-controller@a00000 { >>>>>> + compatible =3D "ti,am62l-event-mux-router"; >>>>>> + reg =3D <0xa00000 0x400>; >>>>>> + #mux-control-cells =3D <1>; >>>>>> + >>>>>> + /* Mux Register addresses: 0xa00004 + (J =C3=97 4) */ >>>>>> + /* GPIO0_40 -> BCDMA trigger 15 */ >>>>>> + ti,reg-mask-val =3D <0x40 0x000ff 0x00028>; >>>>>> + idle-states =3D <0>; >>>>>> + }; >>>>>> --=20 >>>>>> 2.34.1 >>>>>>=20 >>>>=20 >> >=20