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Fri, 22 May 2026 02:17:41 -0700 (PDT) X-Received: by 2002:a05:6300:6d8d:10b0:3b2:8675:47ef with SMTP id adf61e73a8af0-3b328ed49damr1680096637.45.1779441461364; Fri, 22 May 2026 02:17:41 -0700 (PDT) Received: from [10.92.193.94] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84165003369sm1548246b3a.57.2026.05.22.02.17.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 May 2026 02:17:41 -0700 (PDT) Message-ID: <1cf87303-2394-454b-9541-4a3ea4f3ff4a@oss.qualcomm.com> Date: Fri, 22 May 2026 14:47:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] dt-bindings: PCI: qcom: Document the Eliza PCIe Controller To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260521-eliza-v1-0-97cdbe88389d@oss.qualcomm.com> <20260521-eliza-v1-2-97cdbe88389d@oss.qualcomm.com> <20260522-calm-bug-of-kindness-2dfae2@quoll> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20260522-calm-bug-of-kindness-2dfae2@quoll> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: WBnfhxnQ0D_UwUpJPzIwAvByl5xtLPGO X-Authority-Analysis: v=2.4 cv=Zekt8MVA c=1 sm=1 tr=0 ts=6a101f37 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=2kbbHuhoKpOpG5pfR5YA:9 a=YgbPQC_rjE-wQlsd:21 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDA5MiBTYWx0ZWRfX5pLwdjhk3srz /HKr3W1XqBcjbDjsWCcuy/6QtB9CV+5P1+4fo+ngU6gEF5CcJzab4zaY8/3cnVvMoQbWSKIe80e fOvpPrGZ6kz43lGCmju119ma4LBqJfnMcIlRIaCBVmeqtW4SYqckiCLY1HZIz/yif6Af4vRr2Yf nqT3cnlyIR9xM2U92nj+quC2upuorkgcETzIVr55wpMIn4I+ykLpw2410eo6Fi4LssaYHrZDyxU i/X/zZl7P9Uz9MxPScNiMnKLLkPompKre/CmiQvrI3pTcW2f8uKC++ZDk41//yZ5I/ECR88hKAL AbnPUkdtVhhIzlOqs5jGbRCzP7tXEivdW2NYj/b8ap9fMukcnyuybIdrK1hWeiTSNXsXYgukotv PEsIyD/3ipPe7VbYP7FJP+Bx/Qf1u83fvCvwhX1dntmIPt6vV0xl32AycA4mIwV4pc5QeNkTnqx iDPx410Ibv4fZjsC7cQ== X-Proofpoint-GUID: WBnfhxnQ0D_UwUpJPzIwAvByl5xtLPGO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220092 On 5/22/2026 12:20 PM, Krzysztof Kozlowski wrote: > On Thu, May 21, 2026 at 07:35:30PM +0530, Krishna Chaitanya Chundru wrote: >> +description: >> + Qualcomm ELIZA SoC (and compatible) PCIe root complex controller is based on >> + the Synopsis DesignWare PCIe IP. >> + >> +properties: >> + compatible: >> + const: qcom,pcie-eliza > All new pcie compatibles moved to correct format. Ack, I will change it to qcom,elize-pcie >> + >> + reg: >> + minItems: 5 >> + maxItems: 6 >> + >> + reg-names: >> + minItems: 5 >> + items: >> + - const: parf # Qualcomm specific registers >> + - const: dbi # DesignWare PCIe registers >> + - const: elbi # External local bus interface registers >> + - const: atu # ATU address space >> + - const: config # PCIe configuration space >> + - const: mhi # MHI registers >> + >> + clocks: >> + maxItems: 7 >> + >> + clock-names: >> + items: >> + - const: aux # Auxiliary clock >> + - const: cfg # Configuration clock >> + - const: bus_master # Master AXI clock >> + - const: bus_slave # Slave AXI clock >> + - const: slave_q2a # Slave Q2A clock >> + - const: ddrss_sf_tbu # PCIe SF TBU clock >> + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock >> + >> + interrupts: >> + minItems: 8 > This should not be flexible. Neither 'reg'. ack I will remove minItems >> + maxItems: 9 >> + >> + interrupt-names: >> + minItems: 8 >> + items: >> + - const: msi0 >> + - const: msi1 >> + - const: msi2 >> + - const: msi3 >> + - const: msi4 >> + - const: msi5 >> + - const: msi6 >> + - const: msi7 >> + - const: global >> + >> + resets: >> + maxItems: 2 >> + >> + reset-names: >> + items: >> + - const: pci # PCIe core reset >> + - const: link_down # PCIe link down reset >> + >> +required: >> + - power-domains >> + - resets >> + - reset-names >> + >> +allOf: >> + - $ref: qcom,pcie-common.yaml# >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + >> + soc { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + pcie@1c00000 { >> + compatible = "qcom,pcie-eliza"; >> + reg = <0 0x01c00000 0 0x3000>, >> + <0 0x40000000 0 0xf1d>, >> + <0 0x40000f20 0 0xa8>, >> + <0 0x40001000 0 0x1000>, >> + <0 0x40100000 0 0x100000>; >> + reg-names = "parf", "dbi", "elbi", "atu", "config"; >> + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, >> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>; >> + >> + bus-range = <0x00 0xff>; >> + device_type = "pci"; >> + linux,pci-domain = <0>; >> + num-lanes = <1>; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, >> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, >> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a", >> + "ddrss_sf_tbu", >> + "cnoc_sf_axi"; >> + >> + dma-coherent; >> + >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + interrupt-names = "msi0", "msi1", "msi2", "msi3", >> + "msi4", "msi5", "msi6", "msi7", "global"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ >> + <0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ >> + <0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ >> + <0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ >> + >> + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; >> + interconnect-names = "pcie-mem", "cpu-pcie"; >> + >> + iommu-map = <0x0 &apps_smmu 0x1480 0x1>, >> + <0x100 &apps_smmu 0x1481 0x1>; >> + >> + pinctrl-0 = <&pcie0_default_state>; >> + pinctrl-names = "default"; >> + >> + power-domains = <&gcc GCC_PCIE_0_GDSC>; >> + >> + resets = <&gcc GCC_PCIE_0_BCR>, >> + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; >> + reset-names = "pci", >> + "link_down"; >> + > Drop stray blank line. ack. - Krishna Chaitanya. >> + }; >> + }; >> >> -- >> 2.34.1 >>