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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43961826cd4sm4296145e9.24.2025.02.12.18.42.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2025 18:42:11 -0800 (PST) Message-ID: <1cf8d5a5-bf3e-4667-bc6a-d1b1d662d822@citrix.com> Date: Thu, 13 Feb 2025 02:42:10 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC] Circumventing FineIBT Via Entrypoints To: Jann Horn Cc: jmill@asu.edu, joao@overdrivepizza.com, kees@kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org, luto@kernel.org, samitolvanen@google.com, "Peter Zijlstra (Intel)" References: Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 13/02/2025 2:09 am, Jann Horn wrote: > On Thu, Feb 13, 2025 at 2:31 AM Andrew Cooper wrote: >>>> Assuming this is an issue you all feel is worth addressing, I will >>>> continue working on providing a patch. I'm concerned though that the >>>> overhead from adding a wrmsr on both syscall entry and exit to >>>> overwrite and restore the KERNEL_GS_BASE MSR may be quite high, so >>>> any feedback in regards to the approach or suggestions of alternate >>>> approaches to patching are welcome :) >>> Since the kernel, as far as I understand, uses FineIBT without >>> backwards control flow protection (in other words, I think we assume >>> that the kernel stack is trusted?), >> This is fun indeed. Linux cannot use supervisor shadow stacks because >> the mess around NMI re-entrancy (and IST more generally) requires ROP >> gadgets in order to function safely. Implementing this with shadow >> stacks active, while not impossible, is deemed to be prohibitively >> complicated. >> >> Linux's supervisor shadow stack support is waiting for FRED support, >> which fixes both the NMI re-entrancy problem, and other exceptions >> nesting within NMIs, as well as prohibiting the use of the SWAPGS >> instruction as FRED tries to make sure that the correct GS is always in >> context. >> >> But, FRED support is slated for PantherLake/DiamondRapids which haven't >> shipped yet, so are no use to the problem right now. >> >>> could we build a cheaper >>> check on that basis somehow? For example, maybe we could do something like: >>> >>> ``` >>> endbr64 >>> test rsp, rsp >>> js slowpath >>> swapgs >>> ``` >> I presume it's been pointed out already, but there are 3 related >> entrypoints here. SYSCALL64 which is discussed, SYSCALL32 and SYSENTER >> which are related. >> >> But, any other IDT entry is in a similar bucket. If we're corrupting a >> function pointer or return address to redirect here, then the check of >> CS(%rsp) to control the conditional SWAPGS is an OoB read in the callers >> stack frame. >> >> For IDT entries, checking %rsp is reasonable, because userspace can't >> forge a kernel-like %rsp. However, SYSCALL64 specifically leaves %rsp >> entirely attacker controlled (and even potentially non-canonical), so >> I'm wondering what you hand in mind for the slowpath to truly >> distinguish kernel context from user context? > Hm, yeah, that seems hard - maybe the best we could do is to make sure > that the inactive gsbase has the correct value for our CPU's kernel > gsbase? Kinda like a paranoid_entry, except more painful because we'd > first have to figure out a place to spill registers to before we can > start using stuff like rdmsr... Then a function pointer overwrite > might still turn into returning to userspace with a sysret with GPRs > full of kernel pointers, but at least we wouldn't run off of a bogus > gsbase anymore? Thinking about this some more, I think it's impossible to distinguish. One of the many sharp edges of SYSCALL (and SYSENTER for that matter) is that they're instructions expected to be only be used by userspace, but that be executed in supervisor too[1].  They're asymmetric with their SYSRET (and SYSEXIT) counterparts which are CPL0 instructions that strictly transition into CPL3. The SYSCALL behaviour TLDR is:     %rcx = %rip     %r11 = %eflags     %cs = fixed attr     %ss = fixed attr     %rip = MSR_LSTAR which means that %rcx (old rip) is the only piece of state which userspace can't feasibly forge (and therefore could distinguish a SYSCALL from user vs kernel mode), yet if we're talking about a JOP chain to get here, then %rcx is under attacker control too. There are a variety of solutions to this problem that involve not using %gs for per-cpu data.  I also expect that to be wholly unpopular and dismissed as an approach. ~Andrew [1] No-one back then was brave enough to design CPL3-only instructions.