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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b6a76b77bf6sm7309840a12.41.2025.10.20.03.11.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Oct 2025 03:11:18 -0700 (PDT) Message-ID: <1d2b6c69-4ea8-472b-a18d-0bd39042184c@oss.qualcomm.com> Date: Mon, 20 Oct 2025 18:11:11 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/9] clk: qcom: rpmh: Add support for Kaanapali rpmh clocks To: Jingyi Wang , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com References: <20250924-knp-clk-v1-0-29b02b818782@oss.qualcomm.com> <20250924-knp-clk-v1-4-29b02b818782@oss.qualcomm.com> From: "Aiqun(Maria) Yu" Content-Language: en-US In-Reply-To: <20250924-knp-clk-v1-4-29b02b818782@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: vLVDmRPmTH0XbzGUiv9RaAGg8AFbRNeL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyNyBTYWx0ZWRfXxjt7Cr24m4d3 y5aDKoeC7XlpEVYkNhTBqejyAt0biT+luKoPtYaXALq9XVhTsejvNFL03ln4gbRZ14eoeU4+wfp eGNJlj8VKqcKNr1XU/ixAER4BRy5e4tjAHSrZKrAkhOSxY/Jv0G7Qu9TwZA48H7CkQTRED5D4Yo XyRS1+UhZfT+vLQGj00d7dJ0temIswZ551wGVmeasoJdxnP4mPUhjcV70/fJwDUdO7nxmPtSn/P welQ33+nVzZxjaygXWK1JM68+1/1VBB914JIZWt6I5vHVs+rolvlyzh0n5435Km+pzMVzrk78UK Vn+Ceo3tjkTMtcR4n98fJusH44np8RbJ37lKSYkAIWFAiX8IC1LorctDUVZu36g7ByJiRbTgl7C oYrzqOkkKve/csGPVECuPucDaZuS9A== X-Proofpoint-GUID: vLVDmRPmTH0XbzGUiv9RaAGg8AFbRNeL X-Authority-Analysis: v=2.4 cv=EYjFgfmC c=1 sm=1 tr=0 ts=68f60ac8 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=1BWIhq4ta8SIVIyFiOkA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-20_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1011 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180027 On 9/25/2025 6:58 AM, Jingyi Wang wrote: > From: Taniya Das > > Add the RPMH clocks present in Kaanapali SoC. > > Signed-off-by: Taniya Das > Signed-off-by: Jingyi Wang > --- > drivers/clk/qcom/clk-rpmh.c | 39 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index 63c38cb47bc4..6b1f24ee66d5 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -395,6 +395,16 @@ DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1); > DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1); > DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1); > > +DEFINE_CLK_RPMH_VRM(c1a_e0, _a, "C1A_E0", 1); > +DEFINE_CLK_RPMH_VRM(c2a_e0, _a, "C2A_E0", 1); > +DEFINE_CLK_RPMH_VRM(c3a_e0, _a2, "C3A_E0", 2); > +DEFINE_CLK_RPMH_VRM(c4a_e0, _a2, "C4A_E0", 2); > +DEFINE_CLK_RPMH_VRM(c5a_e0, _a2, "C5A_E0", 2); > +DEFINE_CLK_RPMH_VRM(c6a_e0, _a2, "C6A_E0", 2); > +DEFINE_CLK_RPMH_VRM(c7a_e0, _a2, "C7A_E0", 2); > +DEFINE_CLK_RPMH_VRM(c8a_e0, _a2, "C8A_E0", 2); > +DEFINE_CLK_RPMH_VRM(c11a_e0, _a4, "C11A_E0", 4); > + > DEFINE_CLK_RPMH_BCM(ce, "CE0"); > DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); > DEFINE_CLK_RPMH_BCM(ipa, "IP0"); > @@ -900,6 +910,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = { > .num_clks = ARRAY_SIZE(glymur_rpmh_clocks), > }; > > +static struct clk_hw *kaanapali_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, > + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, > + [RPMH_DIV_CLK1] = &clk_rpmh_c11a_e0_a4.hw, > + [RPMH_LN_BB_CLK1] = &clk_rpmh_c6a_e0_a2.hw, > + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_c6a_e0_a2_ao.hw, > + [RPMH_LN_BB_CLK2] = &clk_rpmh_c7a_e0_a2.hw, > + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_c7a_e0_a2_ao.hw, > + [RPMH_LN_BB_CLK3] = &clk_rpmh_c8a_e0_a2.hw, > + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_c8a_e0_a2_ao.hw, > + [RPMH_RF_CLK1] = &clk_rpmh_c1a_e0_a.hw, > + [RPMH_RF_CLK1_A] = &clk_rpmh_c1a_e0_a_ao.hw, > + [RPMH_RF_CLK2] = &clk_rpmh_c2a_e0_a.hw, > + [RPMH_RF_CLK2_A] = &clk_rpmh_c2a_e0_a_ao.hw, > + [RPMH_RF_CLK3] = &clk_rpmh_c3a_e0_a2.hw, > + [RPMH_RF_CLK3_A] = &clk_rpmh_c3a_e0_a2_ao.hw, > + [RPMH_RF_CLK4] = &clk_rpmh_c4a_e0_a2.hw, > + [RPMH_RF_CLK4] = &clk_rpmh_c4a_e0_a2.hw, > + [RPMH_RF_CLK5_A] = &clk_rpmh_c5a_e0_a2_ao.hw, > + [RPMH_RF_CLK5_A] = &clk_rpmh_c5a_e0_a2_ao.hw, > + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, > +}; > + > +static const struct clk_rpmh_desc clk_rpmh_kaanapali = { > + .clks = kaanapali_rpmh_clocks, > + .num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks), > +}; > + > static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, > void *data) > { > @@ -990,6 +1028,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) > > static const struct of_device_id clk_rpmh_match_table[] = { > { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur}, > + { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali}, > { .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos}, > { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, > { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, > Remind to review this patch. -- Thx and BRs, Aiqun(Maria) Yu