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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af47f861e8bsm98426766b.113.2025.07.24.04.46.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Jul 2025 04:46:31 -0700 (PDT) Message-ID: <1d320aac-e928-4fd0-812c-268a3a943575@oss.qualcomm.com> Date: Thu, 24 Jul 2025 13:46:28 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/17] drm/msm/adreno: Add fenced regwrite support To: Akhil P Oommen , Dmitry Baryshkov Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-7-9347aa5bcbd6@oss.qualcomm.com> <30442713-2990-490a-b076-93c3cfc3901d@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=LdY86ifi c=1 sm=1 tr=0 ts=68821d1a cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=sJC1-YunKCaHe1VmF0sA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI0MDA4OCBTYWx0ZWRfX3FlnxJJAapdz /31Q3CvGI/AV7uFF11RYWgnLHG55HuEWBgGfQuRxcLBYaNxBVJC9Me5YdQbCSWbE3TAV9dtJQ6t 5In3x9TKE/O7JT3DqQTy6pAAAxRjoRXPonVVAmK27QM5DXVaCgxUgrmBpooJQ6IozbW5j301IOo pmQeaZfPTRlfn9snStyQWZP4gZLWzyE6dyvVnFyN99exXZh5wNo3u8M1zRLrpOvT/RsBb4LbQXo V538rAF3dZu15+asvg4NqzqrsYmM6oL98phjVhF1ArslHwchKBhlNLVlHuOmpmljijhnp7zn3jm 7ZHOvnebPQiI+fYdXgzOsvIqoagd7M5NJhe96aEyynNI0smf4FCJVrmyghIkp7akS34Q+4rNLb8 4y7YOnpanRAA33kPqNUP2MOBOfqHU6195jxyeM+hb8Y7a/DS87ns3LvclSye9ZC83VrxyFtd X-Proofpoint-ORIG-GUID: I643DHHiMRE7HijswOQyey3rkjotma9X X-Proofpoint-GUID: I643DHHiMRE7HijswOQyey3rkjotma9X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-24_01,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 suspectscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507240088 On 7/23/25 11:06 PM, Akhil P Oommen wrote: > On 7/22/2025 8:22 PM, Konrad Dybcio wrote: >> On 7/22/25 3:39 PM, Dmitry Baryshkov wrote: >>> On Sun, Jul 20, 2025 at 05:46:08PM +0530, Akhil P Oommen wrote: >>>> There are some special registers which are accessible even when GX power >>>> domain is collapsed during an IFPC sleep. Accessing these registers >>>> wakes up GPU from power collapse and allow programming these registers >>>> without additional handshake with GMU. This patch adds support for this >>>> special register write sequence. >>>> >>>> Signed-off-by: Akhil P Oommen >>>> --- >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 ++++++++++++++++++++++++++++++- >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + >>>> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 20 +++++----- >>>> 3 files changed, 73 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> index 491fde0083a202bec7c6b3bca88d0e5a717a6560..8c004fc3abd2896d467a9728b34e99e4ed944dc4 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> @@ -16,6 +16,67 @@ >>>> >>>> #define GPU_PAS_ID 13 >>>> >>>> +static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) >>>> +{ >>>> + /* Success if !writedropped0/1 */ >>>> + if (!(status & mask)) >>>> + return true; >>>> + >>>> + udelay(10); >>> >>> Why do we need udelay() here? Why can't we use interval setting inside >>> gmu_poll_timeout()? >> >> Similarly here: >> >> [...] >> >>>> + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, >>>> + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) >>>> + return 0; >>>> + >>>> + dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", >>>> + offset); >>>> + >>>> + /* Try again for another 1ms before failing */ >>>> + gpu_write(gpu, offset, value); >>>> + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, >>>> + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) >>>> + return 0; >>>> + >>>> + dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", >>>> + offset); >> >> We may want to combine the two, so as not to worry the user too much.. >> >> If it's going to fail, I would assume it's going to fail both checks >> (unless e.g. the bus is so congested a single write can't go through >> to a sleepy GPU across 2 miliseconds, but that's another issue) > > In case of success, we cannot be sure if the first write went through. > So we should poll separately. You're writing to it 2 (outside fence_status_check) + 2*1000/10 (inside) == 202 times, it really better go through.. If it's just about the write reaching the GPU, you can write it once and read back the register you've written to, this way you're sure that the GPU can observe the write Konrad