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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1f02989bsm373791666b.80.2024.10.28.06.08.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2024 06:08:09 -0700 (PDT) Message-ID: <1d374609-8448-43dc-9eec-2407669ae925@oss.qualcomm.com> Date: Mon, 28 Oct 2024 14:08:06 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] arm64: dts: qcom: qcs615: Add QUPv3 configuration To: Viken Dadhaniya , Konrad Dybcio , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_msavaliy@quicinc.com, quic_anupkulk@quicinc.com References: <20241011103346.22925-1-quic_vdadhani@quicinc.com> <15238992-4ede-4b85-9947-391baaa4c8a9@oss.qualcomm.com> <332f7a0a-d9df-49bd-81d5-cc04c50183b9@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <332f7a0a-d9df-49bd-81d5-cc04c50183b9@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: ERWs9NxD_l3Qtq-Vh0leZo0G_Krbt1Ba X-Proofpoint-ORIG-GUID: ERWs9NxD_l3Qtq-Vh0leZo0G_Krbt1Ba X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280106 On 28.10.2024 12:19 PM, Viken Dadhaniya wrote: > > > On 10/26/2024 1:10 AM, Konrad Dybcio wrote: >> On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: >>> Add DT support for QUPv3 Serial Engines. >>> >>> Co-developed-by: Mukesh Kumar Savaliya >>> Signed-off-by: Mukesh Kumar Savaliya >>> Signed-off-by: Viken Dadhaniya >>> --- >> >> [...] >> >>> +    qup_opp_table: opp-table-qup { >>> +        compatible = "operating-points-v2"; >> >> opp-shared; > > Added in v2. > >> >>> + >>> +        opp-75000000 { >>> +            opp-hz = /bits/ 64 <75000000>; >>> +            required-opps = <&rpmhpd_opp_low_svs>; >>> +        }; >>> + >>> +        opp-100000000 { >>> +            opp-hz = /bits/ 64 <100000000>; >>> +            required-opps = <&rpmhpd_opp_svs>; >>> +        }; >>> + >>> +        opp-128000000 { >>> +            opp-hz = /bits/ 64 <128000000>; >>> +            required-opps = <&rpmhpd_opp_nom>; >>> +        }; >>> +    }; >>> + >>>       psci { >>>           compatible = "arm,psci-1.0"; >>>           method = "smc"; >>> @@ -392,6 +427,24 @@ >>>               #size-cells = <1>; >>>           }; >>>   +        gpi_dma0: qcom,gpi-dma@800000  { >>> +            compatible = "qcom,sdm845-gpi-dma"; >> >> You must define a new compatible for qcs615, sdm845 is used as a fallback >> (so that we don't have to add new driver entries). You will however need >> to submit a separate dt-bindings change. > > We have added sdm845 in compatible due to below comment in driver file > > File: https://github.com/torvalds/linux/blob/81983758430957d9a5cb3333fe324fd70cf63e7e/drivers/dma/qcom/gpi.c#L2284 > >   /* >    * Do not grow the list for compatible devices. Instead use >    * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma >    * (for ee_offset = 0x10000). >    */ > > Do we still require new compatible for qcs615 ? The comment concerns the driver side. All devicetree compatible strings present in the tree must be documented in Documentation/devicetree/bindings/ which is where you should add your one as well. > >> >>> +            reg = <0x0 0x800000 0x0 0x60000>; >>> +            #dma-cells = <3>; >>> +            interrupts = , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     , >>> +                     ; >>> +            dma-channels = <8>; >>> +            dma-channel-mask = <0xf>; >>> +            iommus = <&apps_smmu 0xd6 0x0>; >>> +            status = "disabled"; >> >> Any reason? > > By default, we are disabling all nodes. In the target-specific file, we will update them based on the required use case. > >> >>> +        }; >>> + >>>           qupv3_id_0: geniqup@8c0000 { >>>               compatible = "qcom,geni-se-qup"; >>>               reg = <0x0 0x8c0000 0x0 0x6000>; >>> @@ -400,6 +453,7 @@ >>>                    <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>>               clock-names = "m-ahb", >>>                         "s-ahb"; >>> +            iommus = <&apps_smmu 0xc3 0x0>; >> >> This looks like a separate fix > > One QUP and UART (console) related change has been added as part of the base DTSI. Now, we are adding all remaining QUP and I2C/SPI/UART configurations with IOMMUs and other properties. > > Is there any specific reason to make this a separate fix? Did this work properly before? Konrad