From: Dave Hansen <dave.hansen@intel.com>
To: Rik van Riel <riel@surriel.com>, linux-kernel@vger.kernel.org
Cc: kernel-team@meta.com, dave.hansen@linux.intel.com,
luto@kernel.org, peterz@infradead.org, bp@alien8.de,
x86@kernel.org, nadav.amit@gmail.com, seanjc@google.com,
tglx@linutronix.de, mingo@kernel.org,
Rik van Riel <riel@meta.com>,
stable@kernel.org
Subject: Re: [PATCH v2 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask
Date: Fri, 6 Jun 2025 11:50:16 -0700 [thread overview]
Message-ID: <1d52eb65-0f16-4086-803a-5add6cd56550@intel.com> (raw)
In-Reply-To: <20250606171112.4013261-2-riel@surriel.com>
On 6/6/25 10:10, Rik van Riel wrote:
> +/*
> + * With page table isolation, the user_pcid_flush_mask is used to indicate
> + * that the TLB for a process needs to be flushed when switching to user
> + * space. Broadcast TLB flushing uses more PCIDs, and a larger bitmap.
> + */
> +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
> +# ifdef CONFIG_BROADCAST_TLB_FLUSH
> +# define CR3_AVAIL_PCID_LONGS ((1 << CR3_AVAIL_PCID_BITS) / BITS_PER_LONG)
> +# else
> +# define CR3_AVAIL_PCID_LONGS 1
> +# endif
> +#else
> +# define CR3_AVAIL_PCID_LONGS 0
> +#endif
Just so nobody goes and applies this...
I don't like how this looks. I'd much rather have the code be
concentrating on *bits* of ASID space rather than longs. I'm going to
rework this a bit.
next prev parent reply other threads:[~2025-06-06 18:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-06 17:10 [PATCH v2 0/3] x86/mm: TLB flush fixes Rik van Riel
2025-06-06 17:10 ` [PATCH v2 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask Rik van Riel
2025-06-06 18:50 ` Dave Hansen [this message]
2025-06-06 17:10 ` [PATCH v2 2/3] x86/mm: Fix early boot use of INVPLGB Rik van Riel
2025-06-06 17:10 ` [PATCH v2 3/3] x86/mm: Change cpa_flush() to call flush_kernel_range() directly Rik van Riel
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