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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=StidKfO0 c=1 sm=1 tr=0 ts=69066506 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=rTtKBu4o5onlnI9juXDqsQ==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=DwizH8CuqJI6_-ZSpXwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: YiEZYFyFAAl3ufvooMV6QI9TUa9JHIMD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAxMDE3MSBTYWx0ZWRfXxoz+XQKrkd6L BDkn/qB4Omf6JzQxYC8ijqkvXHHOVa50EY2t4m0dP5P6C+KhpwFrl4OWXPXMEn4kJHq142cYNqI qmv85tqY+6R2/5zuUbVfmiXLymIM3ecKSnEpCC9Ml97Vz27DpOuagWBRJSzJlzV0NgdIMfmpoi8 yZyyD8PZTru4NOpp8fYoRfwsHjUF8s3z3x7gGxsKO/xw6IuutDNAF0+a6SMBnRmUILEycrYIXd5 AXpFDKmL7v+dZhY52JsB0iaaVBFhEsuIFI/dqaztbT/qlUmTv4+krdjc3bRo5ahmjiYUGqAO4Xt H08fTXtBTqGzO+eoKL4JHp2QNSva9ahlDhS4dfQmlsXY9TNJJrN2hAOBuogP6k9atWySzpTHMLZ orsAymYZUh7DzCpZIHp4Jji1h+tx+g== X-Proofpoint-ORIG-GUID: YiEZYFyFAAl3ufvooMV6QI9TUa9JHIMD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-01_05,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511010171 On 11/1/2025 6:27 PM, Rob Clark wrote: > On Fri, Oct 31, 2025 at 4:43 PM Chia-I Wu wrote: >> >> On Mon, Sep 8, 2025 at 1:28 AM Akhil P Oommen wrote: >>> >>> Add the IFPC restore register list and enable IFPC support on Adreno >>> X1-85 gpu. >>> >>> Signed-off-by: Akhil P Oommen >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 68 ++++++++++++++++++++++++++++++- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++-- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + >>> 3 files changed, 79 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..547c046730a9b50a82cc9b27f08a5b1eeb08dced 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { >>> >>> DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); >>> >>> +/* Applicable for X185, A750 */ >>> +static const u32 a750_ifpc_reglist_regs[] = { >>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, >>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, >>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, >>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, >>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, >>> + REG_A6XX_TPL1_NC_MODE_CNTL, >>> + REG_A6XX_SP_NC_MODE_CNTL, >>> + REG_A6XX_CP_DBG_ECO_CNTL, >>> + REG_A6XX_CP_PROTECT_CNTL, >>> + REG_A6XX_CP_PROTECT(0), >>> + REG_A6XX_CP_PROTECT(1), >>> + REG_A6XX_CP_PROTECT(2), >>> + REG_A6XX_CP_PROTECT(3), >>> + REG_A6XX_CP_PROTECT(4), >>> + REG_A6XX_CP_PROTECT(5), >>> + REG_A6XX_CP_PROTECT(6), >>> + REG_A6XX_CP_PROTECT(7), >>> + REG_A6XX_CP_PROTECT(8), >>> + REG_A6XX_CP_PROTECT(9), >>> + REG_A6XX_CP_PROTECT(10), >>> + REG_A6XX_CP_PROTECT(11), >>> + REG_A6XX_CP_PROTECT(12), >>> + REG_A6XX_CP_PROTECT(13), >>> + REG_A6XX_CP_PROTECT(14), >>> + REG_A6XX_CP_PROTECT(15), >>> + REG_A6XX_CP_PROTECT(16), >>> + REG_A6XX_CP_PROTECT(17), >>> + REG_A6XX_CP_PROTECT(18), >>> + REG_A6XX_CP_PROTECT(19), >>> + REG_A6XX_CP_PROTECT(20), >>> + REG_A6XX_CP_PROTECT(21), >>> + REG_A6XX_CP_PROTECT(22), >>> + REG_A6XX_CP_PROTECT(23), >>> + REG_A6XX_CP_PROTECT(24), >>> + REG_A6XX_CP_PROTECT(25), >>> + REG_A6XX_CP_PROTECT(26), >>> + REG_A6XX_CP_PROTECT(27), >>> + REG_A6XX_CP_PROTECT(28), >>> + REG_A6XX_CP_PROTECT(29), >>> + REG_A6XX_CP_PROTECT(30), >>> + REG_A6XX_CP_PROTECT(31), >>> + REG_A6XX_CP_PROTECT(32), >>> + REG_A6XX_CP_PROTECT(33), >>> + REG_A6XX_CP_PROTECT(34), >>> + REG_A6XX_CP_PROTECT(35), >>> + REG_A6XX_CP_PROTECT(36), >>> + REG_A6XX_CP_PROTECT(37), >>> + REG_A6XX_CP_PROTECT(38), >>> + REG_A6XX_CP_PROTECT(39), >>> + REG_A6XX_CP_PROTECT(40), >>> + REG_A6XX_CP_PROTECT(41), >>> + REG_A6XX_CP_PROTECT(42), >>> + REG_A6XX_CP_PROTECT(43), >>> + REG_A6XX_CP_PROTECT(44), >>> + REG_A6XX_CP_PROTECT(45), >>> + REG_A6XX_CP_PROTECT(46), >>> + REG_A6XX_CP_PROTECT(47), >>> +}; >>> + >>> +DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); >>> + >>> static const struct adreno_info a7xx_gpus[] = { >>> { >>> .chip_ids = ADRENO_CHIP_IDS(0x07000200), >>> @@ -1432,12 +1495,14 @@ static const struct adreno_info a7xx_gpus[] = { >>> .inactive_period = DRM_MSM_INACTIVE_PERIOD, >>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | >>> ADRENO_QUIRK_HAS_HW_APRIV | >>> - ADRENO_QUIRK_PREEMPTION, >>> + ADRENO_QUIRK_PREEMPTION | >>> + ADRENO_QUIRK_IFPC, >>> .init = a6xx_gpu_init, >>> .a6xx = &(const struct a6xx_info) { >>> .hwcg = a740_hwcg, >>> .protect = &a730_protect, >>> .pwrup_reglist = &a7xx_pwrup_reglist, >>> + .ifpc_reglist = &a750_ifpc_reglist, >>> .gmu_chipid = 0x7050001, >>> .gmu_cgc_mode = 0x00020202, >>> }, >>> @@ -1466,6 +1531,7 @@ static const struct adreno_info a7xx_gpus[] = { >>> .a6xx = &(const struct a6xx_info) { >>> .protect = &a730_protect, >>> .pwrup_reglist = &a7xx_pwrup_reglist, >>> + .ifpc_reglist = &a750_ifpc_reglist, >>> .gmu_chipid = 0x7090100, >>> .gmu_cgc_mode = 0x00020202, >>> .bcms = (const struct a6xx_bcm[]) { >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> index 76dd78f5c48ea818a2aa209e0c0c88bc5e8f4e06..91a2a82c4f388ca6b052172efdd7255165f3c04a 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> @@ -828,11 +828,10 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) >>> u32 *dest = (u32 *)&lock->regs[0]; >>> int i; >>> >>> - reglist = adreno_gpu->info->a6xx->pwrup_reglist; >>> - >>> lock->gpu_req = lock->cpu_req = lock->turn = 0; >>> - lock->ifpc_list_len = 0; >>> - lock->preemption_list_len = reglist->count; >>> + >>> + reglist = adreno_gpu->info->a6xx->ifpc_reglist; >> This is NULL on X1-45 and causes >> >> [ 8.795603] Unable to handle kernel NULL pointer dereference at >> virtual address 0000000000000008 > > Hmm, this is probably going to happen on all a7xx which don't have > IFPC from the looks of it. > > We should either check for the IFPC quirk.. or maybe just drop the > quirk and decide whether IFPC is supported based on ifpc_reglist != > NULL? > > (That said, we probably do want to have IFPC enabled for x1-45) We should add a check for IFPC quirk here. Chia, do you plan to send a fix? To enable IFPC, we can just add a750_ifpc_reglist_regs[] to adreno_gpu->info->a6xx->ifpc_reglist and enable the IFPC quirk. -Akhil. > > BR, > -R > >>> + lock->ifpc_list_len = reglist->count; >>> >>> /* >>> * For each entry in each of the lists, write the offset and the current >>> @@ -843,6 +842,14 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) >>> *dest++ = gpu_read(gpu, reglist->regs[i]); >>> } >>> >>> + reglist = adreno_gpu->info->a6xx->pwrup_reglist; >>> + lock->preemption_list_len = reglist->count; >>> + >>> + for (i = 0; i < reglist->count; i++) { >>> + *dest++ = reglist->regs[i]; >>> + *dest++ = gpu_read(gpu, reglist->regs[i]); >>> + } >>> + >>> /* >>> * The overall register list is composed of >>> * 1. Static IFPC-only registers >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >>> index 124c63c4615930b00c64e488a498163ae35afccd..0b17d36c36a9567e6afa4269ae7783ed3578e40e 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >>> @@ -45,6 +45,7 @@ struct a6xx_info { >>> const struct adreno_reglist *hwcg; >>> const struct adreno_protect *protect; >>> const struct adreno_reglist_list *pwrup_reglist; >>> + const struct adreno_reglist_list *ifpc_reglist; >>> u32 gmu_chipid; >>> u32 gmu_cgc_mode; >>> u32 prim_fifo_threshold; >>> >>> -- >>> 2.50.1 >>>