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charset="iso-8859-15" Content-ID: <4E099362E089D24ABE337BCC7B201A1D@namprd11.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW3PR11MB4620.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7bde9081-28be-431f-b329-08dbf78903da X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Dec 2023 01:00:04.9904 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jUrfDFQ/8o87ZS71AhrOmQ2gwwvfya5lposfIIv3X9xmYht3yRr974nbj6QF7h9KVyNrmuQWEiyk6We89jS/M45p2iP1CuTaVcMsXWnWmR4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR11MB4668 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thank You for the patch. We noticed a break in the customer board with the latest GOP + this patch. Thank You Khaled=09 On Wed, 2023-12-06 at 18:46 +0000, Paz Zcharya wrote: > There was an assumption that for iGPU there should be a 1:1 mapping > of GGTT to physical address pointing to the framebuffer. > This assumption is not strictly true effective generation 8 or newer. > Fix that by checking GGTT to determine the phys address on gen8+. >=20 > The following algorithm for phys_base should be valid for all > platforms: > 1. Find pte > 2. if(IS_DGFX(i915) && pte & GEN12_GGTT_PTE_LM) mem =3D > i915->mm.regions[INTEL_REGION_LMEM_0] else mem =3D i915- > >mm.stolen_region > 3. phys_base =3D (pte & I915_GTT_PAGE_MASK) - mem->region.start; >=20 > - On older platforms, stolen_region points to system memory, starting > at 0 > - on DG2, it uses lmem region which starts at 0 as well > - on MTL, stolen_region points to stolen-local which starts at > 0x800000 >=20 > Changes from v1: > - Add an if statement for gen7-, where there is a 1:1 mapping >=20 > Signed-off-by: Paz Zcharya > --- >=20 > .../drm/i915/display/intel_plane_initial.c | 64 +++++++++++---- > ---- > 1 file changed, 39 insertions(+), 25 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c > b/drivers/gpu/drm/i915/display/intel_plane_initial.c > index a55c09cbd0e4..7d9bb631b93b 100644 > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > @@ -59,44 +59,58 @@ initial_plane_vma(struct drm_i915_private *i915, > return NULL; > =20 > base =3D round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); > - if (IS_DGFX(i915)) { > + > + if (GRAPHICS_VER(i915) < 8) { > + /* > + * In gen7-, there is a 1:1 mapping > + * between GSM and physical address. > + */ > + phys_base =3D base; > + mem =3D i915->mm.stolen_region; > + } else { > + /* > + * In gen8+, there is no 1:1 mapping between > + * GSM and physical address, so we need to > + * check GGTT to determine the physical address. > + */ > gen8_pte_t __iomem *gte =3D to_gt(i915)->ggtt->gsm; > gen8_pte_t pte; > =20 > gte +=3D base / I915_GTT_PAGE_SIZE; > - > pte =3D ioread64(gte); > - if (!(pte & GEN12_GGTT_PTE_LM)) { > - drm_err(&i915->drm, > - "Initial plane programming missing > PTE_LM bit\n"); > - return NULL; > - } > - > - phys_base =3D pte & I915_GTT_PAGE_MASK; > - mem =3D i915->mm.regions[INTEL_REGION_LMEM_0]; > =20 > - /* > - * We don't currently expect this to ever be placed in > the > - * stolen portion. > - */ > - if (phys_base >=3D resource_size(&mem->region)) { > - drm_err(&i915->drm, > - "Initial plane programming using > invalid range, phys_base=3D%pa\n", > - &phys_base); > - return NULL; > + if (IS_DGFX(i915)) { > + if (!(pte & GEN12_GGTT_PTE_LM)) { > + drm_err(&i915->drm, > + "Initial plane programming > missing PTE_LM bit\n"); > + return NULL; > + } > + mem =3D i915->mm.regions[INTEL_REGION_LMEM_0]; > + } else { > + mem =3D i915->mm.stolen_region; > } > =20 > - drm_dbg(&i915->drm, > - "Using phys_base=3D%pa, based on initial plane > programming\n", > - &phys_base); > - } else { > - phys_base =3D base; > - mem =3D i915->mm.stolen_region; > + phys_base =3D (pte & I915_GTT_PAGE_MASK) - mem- > >region.start; > } > =20 > if (!mem) > return NULL; > =20 > + /* > + * We don't currently expect this to ever be placed in the > + * stolen portion. > + */ > + if (phys_base >=3D resource_size(&mem->region)) { > + drm_err(&i915->drm, > + "Initial plane programming using invalid range, > phys_base=3D%pa\n", > + &phys_base); > + return NULL; > + } > + > + drm_dbg(&i915->drm, > + "Using phys_base=3D%pa, based on initial plane > programming\n", > + &phys_base); > + > size =3D round_up(plane_config->base + plane_config->size, > mem->min_page_size); > size -=3D base;