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Fri, 18 Oct 2024 10:28:33 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49IASWZX000489 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 10:28:32 GMT Received: from [10.217.216.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 18 Oct 2024 03:28:28 -0700 Message-ID: <1d74b699-8463-4885-b30a-d4f1eeb7b3db@quicinc.com> Date: Fri, 18 Oct 2024 15:58:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/14] clk: qcom: gdsc: add separate sleep state collapse vote support To: Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Philipp Zabel , Konrad Dybcio CC: , , , References: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> <20241017-sar2130p-clocks-v1-9-f75e740f0a8d@linaro.org> Content-Language: en-US From: Taniya Das In-Reply-To: <20241017-sar2130p-clocks-v1-9-f75e740f0a8d@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gmhx78ShU4ABUnAIpIG4FaOGi_UceL9P X-Proofpoint-ORIG-GUID: gmhx78ShU4ABUnAIpIG4FaOGi_UceL9P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180066 On 10/17/2024 10:26 PM, Dmitry Baryshkov wrote: > Some platforms use separate collapse vote registers for the active and > sleep states. Extend gdsc_update_collapse_bit() to support separate > collapse_sleep_ctrl register. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/gdsc.c | 8 ++++++++ > drivers/clk/qcom/gdsc.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index fa5fe4c2a2ee7786c2e8858f3e41301f639e5d59..95f8e90a8d25673c8a97a03f92cbdad25c3259db 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -133,6 +133,14 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) > if (ret) > return ret; > > + if (sc->collapse_sleep_ctrl) { > + ret = regmap_update_bits(sc->regmap, sc->collapse_sleep_ctrl, mask, val ? mask : 0); > + if (ret) { > + regmap_update_bits(sc->regmap, reg, mask, val ? 0 : mask); > + return ret; > + } > + } > + Dimtry, based on our discussions with design, we understand that this is a one time setting and can be done from the Global clock controller probe. Thus, this patch can be dropped. /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x62204, 0x0); > return 0; > } > > diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h > index 1e2779b823d1c8ca077c9b4cd0a0dbdf5f9457ef..dab2e31be8f65408d6d29df42ad5105830760d3e 100644 > --- a/drivers/clk/qcom/gdsc.h > +++ b/drivers/clk/qcom/gdsc.h > @@ -19,6 +19,7 @@ struct reset_controller_dev; > * @regmap: regmap for MMIO accesses > * @gdscr: gsdc control register > * @collapse_ctrl: APCS collapse-vote register > + * @collapse_sleep_ctrl: APCS collapse-vote register for the sleep state > * @collapse_mask: APCS collapse-vote mask > * @gds_hw_ctrl: gds_hw_ctrl register > * @cxcs: offsets of branch registers to toggle mem/periph bits in > @@ -37,6 +38,7 @@ struct gdsc { > struct regmap *regmap; > unsigned int gdscr; > unsigned int collapse_ctrl; > + unsigned int collapse_sleep_ctrl; > unsigned int collapse_mask; > unsigned int gds_hw_ctrl; > unsigned int clamp_io_ctrl; > -- Thanks & Regards, Taniya Das.