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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbe7afb953sm441039466b.143.2025.02.21.11.19.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Feb 2025 11:19:17 -0800 (PST) Message-ID: <1d9b661e-0607-4567-b420-5444b643df99@oss.qualcomm.com> Date: Fri, 21 Feb 2025 20:19:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] clk: qcom: videocc: Add support to attach multiple power domains To: Bryan O'Donoghue , Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com> <20250218-videocc-pll-multi-pd-voting-v1-4-cfe6289ea29b@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: RBwmkRx2fq0rfnXENo0PO00fanSnCCXb X-Proofpoint-GUID: RBwmkRx2fq0rfnXENo0PO00fanSnCCXb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-21_07,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502210133 On 18.02.2025 4:46 PM, Bryan O'Donoghue wrote: > On 18/02/2025 14:26, Jagadeesh Kona wrote: >> During boot-up, the PLL configuration might be missed even after >> calling pll_configure() from the clock controller probe. This can >> happen because the PLL is connected to one or more rails that are >> turned off, and the current clock controller code cannot enable >> multiple rails during probe. Consequently, the PLL may be activated >> with suboptimal settings, causing functional issues. >> >> To properly configure the video PLLs in the probe on SM8450, SM8475, >> SM8550, and SM8650 platforms, the MXC rail must be ON along with MMCX. >> Therefore, add support to attach multiple power domains to videocc on >> these platforms. >> >> Signed-off-by: Jagadeesh Kona >> --- >>   drivers/clk/qcom/videocc-sm8450.c | 4 ++++ >>   drivers/clk/qcom/videocc-sm8550.c | 4 ++++ >>   2 files changed, 8 insertions(+) >> >> diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c >> index f26c7eccb62e7eb8dbd022e2f01fa496eb570b3f..b50a14547336580de88a741f1d33b126e9daa848 100644 >> --- a/drivers/clk/qcom/videocc-sm8450.c >> +++ b/drivers/clk/qcom/videocc-sm8450.c >> @@ -437,6 +437,10 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) >>       struct regmap *regmap; >>       int ret; >>   +    ret = qcom_cc_attach_pds(&pdev->dev, &video_cc_sm8450_desc); >> +    if (ret) >> +        return ret; >> + >>       ret = devm_pm_runtime_enable(&pdev->dev); >>       if (ret) >>           return ret; >> diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c >> index 7c25a50cfa970dff55d701cb24bc3aa5924ca12d..d4b223d1392f0721afd1b582ed35d5061294079e 100644 >> --- a/drivers/clk/qcom/videocc-sm8550.c >> +++ b/drivers/clk/qcom/videocc-sm8550.c >> @@ -542,6 +542,10 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) >>       int ret; >>       u32 sleep_clk_offset = 0x8140; >>   +    ret = qcom_cc_attach_pds(&pdev->dev, &video_cc_sm8550_desc); >> +    if (ret) >> +        return ret; >> + >>       ret = devm_pm_runtime_enable(&pdev->dev); >>       if (ret) >>           return ret; >> > > What's the difference between doing the attach here or doing it in really_probe() ? > > There doesn't seem to be any difference except that we will have an additional delay introduced. > > Are you describing a race condition ? > > I don't see _logic_ here to moving the call into the controller's higher level probe. > > Can you describe some more ? I think this is a sane course of action: 1. associate pll config with the pll (treewide change) 2. add a generic pll_configure call that parses the type 3. store PLLs to be configured in an array of dt-bindings indices 4. move PLL configuration to really_probe 5. move RPM enablement to really_probe, make it conditional to limit resource waste on e.g. gcc 6. move attaching GDSCs to really_probe Konrad