From: "Chen, Yu C" <yu.c.chen@intel.com>
To: K Prateek Nayak <kprateek.nayak@amd.com>
Cc: <pan.deng@intel.com>, <mingo@kernel.org>,
<linux-kernel@vger.kernel.org>, <tianyou.li@intel.com>,
<tim.c.chen@linux.intel.com>, <peterz@infradead.org>
Subject: Re: [PATCH 3/3] x86/sbm: Derive leaf granularity from LLC cacheinfo instead of topology domain
Date: Tue, 12 May 2026 17:29:40 +0800 [thread overview]
Message-ID: <1dab1e94-43d1-4528-986d-0bed73e84bae@intel.com> (raw)
In-Reply-To: <d8bf62c3-8f4a-43f3-b7f5-a3213722f6dd@amd.com>
Hi Prateek,
On 5/11/2026 3:48 PM, K Prateek Nayak wrote:
>> - if (!amd_fill_cpuid4_info(llc_index, &id4))
>> + if (!amd_fill_cpuid4_info(llc_index, &id4)) {
>> c->topo.llc_id = get_cache_id(c->topo.apicid, &id4);
>> + if (c == &boot_cpu_data)
>> + arch_sbm_shift = get_count_order(1 + id4.eax.split.num_threads_sharing);
>> + }
>
> So I'm slightly skeptical on AMD's heterogenous processors based systems
> getting this right but I have to get my hands on one to confirm.
>
> Either ways, it seems like an AMD specific problem that I'll chase down
> if it exists but this should be fine from testing perspective on your
> system.
>
Right, this reminds me that Intel's heterogeneous (hybrid) processors
might also need to be accounted for if the platform has multiple LLCs.
>> struct sbm *sbm_alloc(void)
>> {
>> - unsigned int nr = arch_sbm_leafs;
>> - unsigned int nbits = 1U << arch_sbm_shift;
>> - unsigned int nlongs = BITS_TO_LONGS(nbits);
>> - struct sbm_root *root = kzalloc_flex(*root, leafs, nr);
>> + unsigned int nr;
>> + unsigned int nbits;
>> + unsigned int nlongs;
>> + struct sbm_root *root;
>> struct sbm_leaf *leaf;
>> +
>> + if (!arch_sbm_shift) {
>> + unsigned int max_idx = num_possible_cpus();
>> +
>> + /*
>> + * unsigned long is the base unit for bitmap in sbm_leaf.
>> + * Use that for default bitmap size for compact bitmap
>> + * without unused bits.
>> + */
>> + arch_sbm_shift = BYTES_TO_BITS(sizeof(unsigned long));
>> + arch_sbm_leafs = 1 + (max_idx >> arch_sbm_shift);
>> + arch_sbm_mask = (1 << arch_sbm_shift) - 1;
>> + arch_sbm_bits = arch_sbm_shift;
>
> Side note:
>
> So while chasing sbitmap, I realized there are some users of sbitmap out
Thanks for pointing it out. I took a look at sbitmap; it seems to
provide cache-friendly bit allocation strategy for different CPUs.
This seems to be a bit different usage model from sbm, which aims
to provide a 1:1 mapping between a CPU and its corresponding bit
in a mask in a cache-friendly manner. That said, the allocation
logic could be reused between sbitmap and sbm IMO.
> there that are essentially using its minimal functionality that smb
> provides and can be converted over to save an extra cacheline worth of
> overhead.
>
> Does it make sense to keep the arch_sbm_* stuff specific to the
> scheduler and allow wider use of sbm for any sparse bitmap usage?
>
Yes, I think this is feasible. We can introduce
struct sbm *sbm_alloc(unsigned int max_idx, unsigned int leaf_bits)
to allow reuse by other non-scheduler components.
>> + }
>> +
>> + nr = arch_sbm_leafs;
>> + nbits = 1U << arch_sbm_shift;
>> + nlongs = BITS_TO_LONGS(nbits);
>> + root = kzalloc_flex(*root, leafs, nr);
>> if (!root)
>> return NULL;
>>
>
> My QEMU has suddenly refused to boot after the conversion to cache
> properties leaf changes so I'll try to see why that is the case.
>
Thanks, I haven't tested on VM yet, let me take a look.
thanks,
Chenyu
next prev parent reply other threads:[~2026-05-12 9:29 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-21 6:10 [PATCH v2 0/4] sched/rt: mitigate root_domain cache line contention Pan Deng
2025-07-21 6:10 ` [PATCH v2 1/4] sched/rt: Optimize cpupri_vec layout to mitigate " Pan Deng
2026-03-20 10:09 ` Peter Zijlstra
2026-03-24 9:36 ` Deng, Pan
2026-03-24 12:11 ` Peter Zijlstra
2026-03-27 10:17 ` Deng, Pan
2026-04-02 10:37 ` Deng, Pan
2026-04-02 10:43 ` Peter Zijlstra
2026-04-08 10:16 ` Chen, Yu C
2026-04-09 11:47 ` Deng, Pan
2025-07-21 6:10 ` [PATCH v2 2/4] sched/rt: Restructure root_domain to reduce cacheline contention Pan Deng
2026-03-20 10:18 ` Peter Zijlstra
2025-07-21 6:10 ` [PATCH v2 3/4] sched/rt: Split root_domain->rto_count to per-NUMA-node counters Pan Deng
2026-03-20 10:24 ` Peter Zijlstra
2026-03-23 18:09 ` Tim Chen
2026-03-24 12:16 ` Peter Zijlstra
2026-03-24 22:40 ` Tim Chen
2025-07-21 6:10 ` [PATCH v2 4/4] sched/rt: Split cpupri_vec->cpumask to per NUMA node to reduce contention Pan Deng
2026-03-20 12:40 ` Peter Zijlstra
2026-03-23 18:45 ` Tim Chen
2026-03-24 12:00 ` Peter Zijlstra
2026-03-31 5:37 ` Chen, Yu C
2026-03-31 10:19 ` K Prateek Nayak
2026-04-02 3:15 ` Chen, Yu C
2026-04-02 4:41 ` K Prateek Nayak
2026-04-02 10:55 ` Peter Zijlstra
2026-04-02 11:06 ` K Prateek Nayak
2026-04-03 5:46 ` Chen, Yu C
2026-04-03 8:13 ` K Prateek Nayak
2026-04-07 20:35 ` Tim Chen
2026-04-08 3:06 ` K Prateek Nayak
2026-04-08 11:35 ` Chen, Yu C
2026-04-08 15:52 ` K Prateek Nayak
2026-04-09 5:17 ` K Prateek Nayak
2026-04-09 23:09 ` Tim Chen
2026-04-10 5:51 ` Chen, Yu C
2026-04-10 6:02 ` K Prateek Nayak
2026-05-10 15:59 ` [PATCH v2 1/4] sched/rt: Optimize cpupri_vec layout to mitigate cache line contention Chen Yu
2026-05-10 15:59 ` [PATCH 1/3] x86/sbm: Fix domain shift calculation and sbm_find_next_bit() Chen Yu
2026-05-10 15:59 ` [PATCH 2/3] lib/sbm: Use dynamically sized bitmap in sbm_leaf Chen Yu
2026-05-10 15:59 ` [PATCH 3/3] x86/sbm: Derive leaf granularity from LLC cacheinfo instead of topology domain Chen Yu
2026-05-11 7:48 ` K Prateek Nayak
2026-05-12 9:29 ` Chen, Yu C [this message]
2026-04-08 9:25 ` [PATCH v2 4/4] sched/rt: Split cpupri_vec->cpumask to per NUMA node to reduce contention Chen, Yu C
2026-04-08 16:47 ` Tim Chen
2026-03-20 9:59 ` [PATCH v2 0/4] sched/rt: mitigate root_domain cache line contention Peter Zijlstra
2026-03-20 12:50 ` Peter Zijlstra
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