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Tue, 15 Sep 2026 09:38:36 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v5 03/15] iommu/arm-smmu-v3: Add Q_POS() macro Date: Tue, 15 Sep 2026 09:38:15 -0700 Message-ID: <1db9d32df4a59dcac286e7a82bc2704cdd69b8e0.1789446520.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00018070:EE_|CY8PR12MB8066:EE_ X-MS-Office365-Filtering-Correlation-Id: acfb8685-7943-4b00-af38-08df1347db38 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|23010399003|18002099003|22082099003|10067099003|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: todoNaYhuxfmad5k+QkA66tDjQWfjhFFGVntSQbljD/iBCASWiowNPw0+dE/iMWvBvnIp9or3beANVB6nVTPAMCNPH+QmBBLj2Q6R8V6sbDY/A2Xx8Z11TCqVA+C8h9VQBgMsDcuY62+ybaqnD/Wo3NItT7B+HWslZ9+aKv1B2yB4N/QMQKMkMmjNpey85q1tyEbiNtP7FsZNx3LaBssnTZmVFNVcKJvs8FhbSyOKLNXE3dZtAgAx4wgJooCvbAQerHI4IkXe8KSq0xEO5Nwa8jKu7OZfN9C2rV1VXA6k3P9vqC5klG1wDnL/FwNhbPLsUWEC9Xb0kdIfRW09QWqv2+Ggn5GpjtQs942T7lVdimjQAAVAhGe8j8m2AZjLJ5BAGli6XT3h6Emnv9QEhOz+xT4MQ/vmUMRMTOHAGy6n+iKtTW9F5tK+rrwiEpmvyHw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 16:39:04.9616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acfb8685-7943-4b00-af38-08df1347db38 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00018070.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8066 A queue position, the wrap bit combined with the index, is Q_WRP | Q_IDX. It is a (max_n_shift + 1)-bit value that wraps at twice the queue capacity. queue_inc_cons(), queue_sync_cons_ovf(), and queue_inc_prod_n() currently compute such positions by open-coding the two macros at each call site. Add a Q_POS() macro and switch the open-coded sites to it. A subsequent change will build a Q_DIFF() on it, to count the entries that a queue pointer moved past. No functional change intended. Assisted-by: LLM Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 5b89bad71c102..de7e4284658a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -187,6 +187,8 @@ struct arm_vsmmu; #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) +/* A position is Q_WRP | Q_IDX, wrapping at twice the queue capacity */ +#define Q_POS(llq, p) (Q_WRP(llq, p) | Q_IDX(llq, p)) #define Q_OVERFLOW_FLAG (1U << 31) #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) #define Q_ENT(q, p) ((q)->base + \ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 759d0e1126b30..b908a8af31442 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -181,8 +181,8 @@ static void queue_sync_cons_out(struct arm_smmu_queue *q) static void queue_inc_cons(struct arm_smmu_ll_queue *q) { - u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; - q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); + u32 cons = Q_POS(q, q->cons) + 1; + q->cons = Q_OVF(q->cons) | Q_POS(q, cons); } static void queue_sync_cons_ovf(struct arm_smmu_queue *q) @@ -192,8 +192,7 @@ static void queue_sync_cons_ovf(struct arm_smmu_queue *q) if (likely(Q_OVF(llq->prod) == Q_OVF(llq->cons))) return; - llq->cons = Q_OVF(llq->prod) | Q_WRP(llq, llq->cons) | - Q_IDX(llq, llq->cons); + llq->cons = Q_OVF(llq->prod) | Q_POS(llq, llq->cons); queue_sync_cons_out(q); } @@ -218,8 +217,8 @@ static int queue_sync_prod_in(struct arm_smmu_queue *q) static u32 queue_inc_prod_n(struct arm_smmu_ll_queue *q, int n) { - u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n; - return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); + u32 prod = Q_POS(q, q->prod) + n; + return Q_OVF(q->prod) | Q_POS(q, prod); } static void queue_poll_init(struct arm_smmu_device *smmu, -- 2.43.0