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From: Joao Pinto <Joao.Pinto@synopsys.com>
To: Jisheng Zhang <jszhang@marvell.com>, <jingoohan1@gmail.com>,
	<Joao.Pinto@synopsys.com>, <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
Date: Mon, 17 Jul 2017 10:27:44 +0100	[thread overview]
Message-ID: <1df044ef-1daf-0b60-da30-a6a45215f275@synopsys.com> (raw)
In-Reply-To: <20170713103527.1642-1-jszhang@marvell.com>

Hi,

Às 11:35 AM de 7/13/2017, Jisheng Zhang escreveu:
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable it.
> 
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
>  drivers/pci/dwc/pcie-designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
>  	 */
>  	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
>  		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> -		if (val == PCIE_ATU_ENABLE)
> +		if (val & PCIE_ATU_ENABLE)
>  			return;
>  
>  		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> 
Make sense, turn it more accurate. Thanks!

Acked-by: Joao Pinto <jpinto@synopsys.com>

  reply	other threads:[~2017-07-17  9:27 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-13 10:35 Jisheng Zhang
2017-07-17  9:27 ` Joao Pinto [this message]
2017-07-17 19:32   ` Jingoo Han

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