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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b942ef48267sm494734566b.3.2026.03.10.08.15.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2026 08:15:02 -0700 (PDT) Message-ID: <1df08447-0ace-4771-bc1c-b0f8c5d0f9b2@oss.qualcomm.com> Date: Tue, 10 Mar 2026 16:15:00 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] clk: qcom: Add Global Clock controller (GCC) driver for Fillmore To: Aelin Reidel , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht References: <20260308-fillmore-clks-v1-0-976d9a6bebe7@mainlining.org> <20260308-fillmore-clks-v1-3-976d9a6bebe7@mainlining.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260308-fillmore-clks-v1-3-976d9a6bebe7@mainlining.org> Content-Type: text/plain; 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> + > +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { > + .cmd_rcgr = 0x24014, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_5, > + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gcc_sdcc2_apps_clk_src", > + .parent_data = gcc_parent_data_5, > + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .flags = CLK_OPS_PARENT_ENABLE, > + .ops = &clk_rcg2_ops, &clk_rcg2_shared_floor_ops [...] > +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { > + .cmd_rcgr = 0x8702c, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_10, > + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gcc_ufs_phy_axi_clk_src", > + .parent_data = gcc_parent_data_10, > + .num_parents = ARRAY_SIZE(gcc_parent_data_10), > + .ops = &clk_rcg2_ops, > + }, > +}; please check for .enable_safe_parent or something like that in the downstream driver - for all RCGs that have it, use clk_rcg2_shared_ops [...] > +static struct gdsc pcie_0_gdsc = { > + .gdscr = 0x7b004, > + .pd = { > + .name = "pcie_0_gdsc", > + }, > + .pwrsts = PWRSTS_RET_ON, > +}; > + > +static struct gdsc ufs_phy_gdsc = { > + .gdscr = 0x87004, > + .pd = { > + .name = "ufs_phy_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > +static struct gdsc usb30_prim_gdsc = { > + .gdscr = 0x49004, > + .pd = { > + .name = "usb30_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; Your downstream DT also has: HLOS1_VOTE_MMNOC_MMU_TBU_HF[0123] _SF[01] _TBU[01] that all need to be defined and have .flags = VOTABLE Konrad