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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: FIJwSAZbCYCgWBV-Jm_qhzXnnDQfKZNl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE4MDA3OCBTYWx0ZWRfX775EWGJrtzyG 39gvko3T25i+5Pa3MRQHkXTIKCldPb+PC+ggsw3gXhUeYoF/d8SJ8Y3888tzZAOkLEnQA+wCCXP G69Krl1y9ZTlUYAbO7YyO7pOdkDf0wtlBVLuRcci3gSX4n/OGozyeFm0ZDM8DgojnJPnIx25lOp r9NvkEcfTyAJWXK0pxhGnTnXfWJWsD01Y012337x7PqOGORBne/U5FlAPEEy9C8WChEOr7DSPlc CEJoR9JA/Ru5vpJTqt/aaL+W5HIa5SanBQ0Axm2ttWoFbF1OSCcYn+38lHdgPXbYotKoEM2ltyj hUT7gd96Gqwyff5M5tEWXMmqfOm6UZ2Sv+DrdIE30FOUjHZ0ERU7WFsa9C6Xfy99FmBblLj8o6v thQlQ1hCM3rStjQ7fBh3FEhkOGrINRrtuv+LAMTkSfZoE9IuW6kOz6UBwQ1SwkBMYhW1yZmg46K wcFuFpabem2z1WEG1GQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODE4MDA3OCBTYWx0ZWRfXwa9p0/MH/nyY ACcnqyC7GSB8CvjETh5Gyvhbd/4qOlZUzrcExWnmEcB+t5yHq4zGE7DD4qgW8QNk8tZw3L0xY/r bYOcWGizyhc0Uiadn6xVM7Mr510huEM= X-Authority-Analysis: v=2.4 cv=FsU1OWrq c=1 sm=1 tr=0 ts=6a8435b4 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=85NeIpzETsoQluUi9CYA:9 a=QEXdDO2ut3YA:10 a=ZXulRonScM0A:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: FIJwSAZbCYCgWBV-Jm_qhzXnnDQfKZNl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-18_01,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608180078 On 8/10/26 5:42 PM, Dmitry Baryshkov wrote: > The HSIC instances of the chipidea controller runtime-suspend with > their clocks gated whenever the bus is empty. HSIC has no VBUS-style > connect detection: a device (such as an onboard hub coming out of > reset) signals a single connect event, and if the controller is > suspended at that moment the connect is never noticed and the device > never enumerates. [...] > + /* > + * The optional second interrupt is the asynchronous wakeup interrupt > + * of the HSIC instances: without it a bus connect arriving while the > + * runtime-suspended controller has its clocks gated is never seen. > + */ > + wake_irq = platform_get_irq_optional(pdev, 1); > + if (wake_irq > 0) { > + device_init_wakeup(&plat_ci->dev, true); > + ret = dev_pm_set_dedicated_wake_irq(&plat_ci->dev, wake_irq); devm_pm_set_wake_irq()? Konrad