From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4BF3B47D2 for ; Thu, 23 Jul 2026 05:47:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785672; cv=none; b=EEjYe7kRLuW9kbL9TQpdf6Tjkb8htRxzZ7IQ4RruMDm/tMUqRRT6jLuj0ZMUv2bjymsNasah9wQtzeZ9CzmyGHPPxnGErUws8GC5B5jp9KnvbNMMs3Yh5Yxq9Hb3mqkSS/PSF7upOvD0xRV4G8c1hAkLfvPZb5xpVQHQ3qvxuOo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785672; c=relaxed/simple; bh=3dvpUCEmFZLhOdsix3vvI/+dqHzTXke2UNnZ5FtPp1s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EWZAAFhEqRU6tsQpQ0A4phm6adKlNHvvH2gu5ASIfCrt3dxnhMko012bQ0bvegW7z79/i9dng/8BZPUvLfFnBh2jOKvFxeR4gUba3fB07dNgIF3KPb5NxQBFtlalKhqfoyXZVYQqPFtxZMdSM8BRHcN9aS/RGFxI/bbUobSLb5g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P9Y6Zcu+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P9Y6Zcu+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 448511F000E9; Thu, 23 Jul 2026 05:47:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784785671; bh=E7jiGXQqxOrWtbJ+R0BFZod6SdLbHVsUozwK9g4AYsk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=P9Y6Zcu+2N4wgh9GkD2Opesrt9CwiTAidw0HascfGjFjbbFregStcBPa2UUlD0D9p ZD5ONuQkCQ+1EluZ6hkQHSUTiF4OCzrXTpcONV1gI6iXlB+3lSp5m6Cc1+2x7ihLfM WQkN4rupiTmJokzNM5rw9rsb5Qe2OFyKoa+yiPE15oJEWavuB3qVd5PaLRBs4v94oh buQU8Hp3kEJkeHyyd1s7a+QhdZo4oAE2H/DHE+48yEy6lm0PZuSkmzA2dHdgyDWCSz +Rp1gMeYzScto6zRYTmQvstSsLbcVbOciThQcsZN/Uddnd3o0fV3lOrZqGmLDzOZls +zZspmZCsbXig== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: [PATCH v4 3/3] x86/apic: Drop APIC_EILVT_NR_MAX Date: Thu, 23 Jul 2026 11:14:08 +0530 Message-ID: <1e1b30ea5bf521fd2c793951a9e07ca0bd8059ca.1784785046.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Switch to using apic->eilvt_regs_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index c990f403ec7f..dd734c58b780 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) * necessarily a BIOS bug. */ -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) { @@ -354,7 +354,7 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) { unsigned int rsvd, vector; - if (offset >= APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >= apic->eilvt_regs_count) return ~0; rsvd = atomic_read(&eilvt_offsets[offset]); @@ -417,6 +417,9 @@ static __init void init_eilvt(void) if (!apic->eilvt_regs_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD) apic->eilvt_regs_count = APIC_EILVT_NR_AMD_10H; + + if (apic->eilvt_regs_count) + eilvt_offsets = kzalloc_objs(atomic_t, apic->eilvt_regs_count); } /* -- 2.54.0