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Wed, 06 May 2026 21:07:11 -0700 (PDT) X-Received: by 2002:a05:6a00:2347:b0:839:f1c0:13ce with SMTP id d2e1a72fcca58-83a5df4b7d7mr5906147b3a.40.1778126830771; Wed, 06 May 2026 21:07:10 -0700 (PDT) Received: from [10.218.34.110] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83967dbf67fsm7219120b3a.47.2026.05.06.21.07.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 May 2026 21:07:10 -0700 (PDT) Message-ID: <1e294832-724d-451c-87ef-794f9debd905@oss.qualcomm.com> Date: Thu, 7 May 2026 09:37:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] pinctrl: qcom: Unconditionally mark gpio as wakeup enable To: Konrad Dybcio , Bjorn Andersson , Linus Walleij , Neil Armstrong , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260430-enable_wakeup_capable_gpios-v1-1-5de39bf06094@oss.qualcomm.com> <03cd1bbc-6d8e-4819-8cb5-a46a7d58b1b9@oss.qualcomm.com> Content-Language: en-US From: Sneh Mankad In-Reply-To: <03cd1bbc-6d8e-4819-8cb5-a46a7d58b1b9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=XsPK/1F9 c=1 sm=1 tr=0 ts=69fc0ff0 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=43YHA6yz2nHLIAHiA8wA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: d95wlf3W3w0Z9r_MTk6fGHn_kFAZpOOI X-Proofpoint-ORIG-GUID: d95wlf3W3w0Z9r_MTk6fGHn_kFAZpOOI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDAzNyBTYWx0ZWRfX+bZoT0iNT2/+ 1dDRzqBoXvcqmpQ9AvVHZohqT/hHud1sYxUYq0B6tq2EMC2cVVEdCn4+TMhaghia8nnedxKe/ng 9itXVl8W5FhXegsJxgQWvI820dsVKtWvYWMa66d53hK7McZqMOXp7+9gY0KKvOs+6iZdRGJFZQK mfCuxrx9AAFZXu1/WxS02snlpOUddU3ls8WHhKgnKmY1xX54d/RsRoEAdf7Lepyx76orG0mBVHy +Zv1tNFDlvvDTUPahg7By9UyfkBfnLPED/n/Wa9G+p3Wb07puc1jXB8ri27f38vlvIvhWt3BbGz oDt7TFe8Z8M5HD9dW4kHgNlMeO0iIHniFXaTVeNsupXdlciU5R03fIFZUpEEEzkej8Qe4HqDNtR j9r3sO9y/iqNpzNcdCKI3ZdHdIgO0z2hntu3nf20ZznCPdO1HxAWeFYP6fQFL9Fwiw6HgoDXhxw mH7RIQbm2ip2pbX40mA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070037 On 05-May-26 4:13 PM, Konrad Dybcio wrote: > On 4/30/26 7:54 AM, Sneh Mankad wrote: >> The wakeup enable bit needs to be set irrespective of the SoC using PDC or >> MPM as wakeup capable irqchip to allow the GPIO interrupts to be forwarded >> to parent irqchip. >> >> This is set only for PDC irqchip using additional check skip_wake_irqs >> making it impossible for MPM irqchip to detect the GPIO interrupt during >> SoC low power mode since for MPM irqchip the skip_wake_irqs is always >> false. > This describes the impact, but not the reason why this happens. Please > expand on that. > > Konrad Ok Konrad, I will post v3 with proper reasoning mentioned. Thanks, Sneh