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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35e34cece9esm1549105a91.1.2026.04.09.04.33.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Apr 2026 04:33:17 -0700 (PDT) Message-ID: <1e3e0fd7-742b-49cd-b432-da9bd2a0ba7b@oss.qualcomm.com> Date: Thu, 9 Apr 2026 19:33:12 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 17/38] drm/msm/dp: add support to send ACT packets for MST To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar References: <20250825-msm-dp-mst-v3-0-01faacfcdedd@oss.qualcomm.com> <20250825-msm-dp-mst-v3-17-01faacfcdedd@oss.qualcomm.com> <46d97aec-9f46-42bd-8725-2c236ffd13ba@oss.qualcomm.com> <4cb29e7a-9a75-4f8a-9036-c96e9190b7b0@oss.qualcomm.com> <4rhd6qlj4jevrnj2zqctqrcbpkvcalk5qmr3ryuk6ewwa7e35p@o7xzhuzfsms2> Content-Language: en-US From: Yongxing Mou In-Reply-To: <4rhd6qlj4jevrnj2zqctqrcbpkvcalk5qmr3ryuk6ewwa7e35p@o7xzhuzfsms2> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDEwMyBTYWx0ZWRfXwEF71icux43T oR5eQhPMjFVHBXmelP+rePn9j16al3mRzyk3Xiz/zdlaqn4RtbUZKP8QicwsUf69KiP4WgTUj7q OiNgLsv/VATyVHq7BA2NCkcxkP27/vvWVMm8NomYDVbjUXJ/lcOErd7Q8wIA+LqNZTvGeZZlbYP 5UXvW/6TxdZJT5t+vO5mAKUUedJQy4vC3j5w+DVGGIz0i6S6bCm44KOvEinq8nQAUiA+3230X5t 20inpmPx2pHCV5Ed10l1i4EHZQaV/XyT5QdA1Mlof7wbDOai0BnkEGCkOAg0W1Fdqx4LmnPKiI7 P7B/pYcNF+1zRjJI5jLRWu12kzpmUguon9Z1Y3B+P0nu1L4MdfOEP0QEhw+FBFl7YAbXbjLgdSf n2oCGDMXRysqgEbeiVC5pACUdg7gEyHHqQCzgIRLTmoYrIqIir4a7we/2T7mNXNjmymogHKfhEF hGkwjsQuUgmONxP2tTg== X-Authority-Analysis: v=2.4 cv=SsWgLvO0 c=1 sm=1 tr=0 ts=69d78e7f cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=YxuP5ldsg-JQntm2Dv8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: MzEhSlKLIPjFTd3cUnrbe1JBfo6fvV-y X-Proofpoint-ORIG-GUID: MzEhSlKLIPjFTd3cUnrbe1JBfo6fvV-y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_03,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 impostorscore=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090103 On 4/1/2026 7:27 PM, Dmitry Baryshkov wrote: > On Wed, Apr 01, 2026 at 02:55:32PM +0800, Yongxing Mou wrote: >> >> >> On 4/1/2026 2:47 PM, Dmitry Baryshkov wrote: >>> On 01/04/2026 09:44, Yongxing Mou wrote: >>>> >>>> >>>> On 8/26/2025 5:10 AM, Dmitry Baryshkov wrote: >>>>> On Mon, Aug 25, 2025 at 10:16:03PM +0800, Yongxing Mou wrote: >>>>>> From: Abhinav Kumar >>>>>> >>>>>> Whenever virtual channel slot allocation changes, the DP >>>>>> source must send the action control trigger sequence to notify >>>>>> the sink about the same. This would be applicable during the >>>>>> start and stop of the pixel stream. Add the infrastructure >>>>>> to be able to send ACT packets for the DP controller when >>>>>> operating in MST mode. >>>>>> >>>>>> Signed-off-by: Abhinav Kumar >>>>>> Signed-off-by: Yongxing Mou >>>>>> --- >>>>>>   drivers/gpu/drm/msm/dp/dp_ctrl.c    | 39 >>>>>> +++++++++++++++++++++++++ + +++++++++-- >>>>>>   drivers/gpu/drm/msm/dp/dp_ctrl.h    |  4 ++-- >>>>>>   drivers/gpu/drm/msm/dp/dp_display.c |  3 ++- >>>>>>   drivers/gpu/drm/msm/dp/dp_display.h |  1 + >>>>>>   drivers/gpu/drm/msm/dp/dp_reg.h     |  2 ++ >>>>>>   5 files changed, 44 insertions(+), 5 deletions(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>>>> b/drivers/gpu/drm/msm/ dp/dp_ctrl.c >>>>>> index 608a1a077301b2ef3c77c271d873bb4364abe779..16e5ed58e791971d5dca3077cbb77bfcc186505a >>>>>> 100644 >>>>>> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>>>> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>>>> @@ -142,6 +142,7 @@ struct msm_dp_ctrl_private { >>>>>>       bool core_clks_on; >>>>>>       bool link_clks_on; >>>>>>       bool stream_clks_on[DP_STREAM_MAX]; >>>>>> +    bool mst_active; >>>>>>   }; >>>>>>   static inline u32 msm_dp_read_ahb(const struct >>>>>> msm_dp_ctrl_private *ctrl, u32 offset) >>>>>> @@ -227,6 +228,32 @@ static int >>>>>> msm_dp_aux_link_configure(struct drm_dp_aux *aux, >>>>>>       return 0; >>>>>>   } >>>>>> +void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) >>>>>> +{ >>>>>> +    struct msm_dp_ctrl_private *ctrl; >>>>>> +    bool act_complete; >>>>>> + >>>>>> +    ctrl = container_of(msm_dp_ctrl, struct >>>>>> msm_dp_ctrl_private, msm_dp_ctrl); >>>>>> + >>>>>> +    if (!ctrl->mst_active) >>>>>> +        return; >>>>>> + >>>>>> +    msm_dp_write_link(ctrl, REG_DP_MST_ACT, 0x1); >>>>>> +    /* make sure ACT signal is performed */ >>>>>> +    wmb(); >>>>>> + >>>>>> +    msleep(20); /* needs 1 frame time */ >>>>>> + >>>>>> +    act_complete = msm_dp_read_link(ctrl, REG_DP_MST_ACT); >>>>>> + >>>>>> +    if (!act_complete) >>>>>> +        drm_dbg_dp(ctrl->drm_dev, "mst ACT trigger complete >>>>>> SUCCESS\n"); >>>>>> +    else >>>>>> +        drm_dbg_dp(ctrl->drm_dev, "mst ACT trigger complete >>>>>> failed\n"); >>>>> >>>>> Shouldn't it return an error if the register dind't latch? Also, >>>>> shouldn't we set mst_active only if the write went through? >>>>> >>>> In some cases, MST still works correctly even when the ACT trigger >>>> fails; here refer to the downstream implementation. >>> >>> I don't think it is a good idea. It would be better to signal this to >>> the user and rollback the MST configuration (as in the case of any other >>> error). >>> >>> I will change my mind if you point out i915, amdgpu or nouveau drivers >>> ignoring the ACT issues. >>> >> Sure. Until I can find more convincing evidence, I will make the changes as >> requested. > > Or you can point out the relevant part of the standard. > Emm ,the DP HPG only specifies that an MST_ACT needs to be issued, and does not require validating its contents. This appears to be a Qualcomm‑specific hardware register, not a generic one.