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Fri, 13 Dec 2024 09:18:19 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BD9IIAe019113 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 09:18:18 GMT Received: from [10.239.132.152] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 01:18:16 -0800 Message-ID: <1e99294f-b528-4cf7-a0e0-3d78221e6982@quicinc.com> Date: Fri, 13 Dec 2024 17:18:14 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] coresight-etm4x: add isb() before reading the TRCSTATR To: Leo Yan CC: , , , , , , References: <20241204112332.3706137-1-quic_yuanfang@quicinc.com> <20241204151650.GA1976757@e132581.arm.com> Content-Language: en-US From: Yuanfang Zhang In-Reply-To: <20241204151650.GA1976757@e132581.arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: p_9MwUObVSA2qo8Me6vwxP0ygYgJGMDg X-Proofpoint-ORIG-GUID: p_9MwUObVSA2qo8Me6vwxP0ygYgJGMDg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 clxscore=1011 bulkscore=0 lowpriorityscore=0 mlxlogscore=902 priorityscore=1501 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130063 On 12/4/2024 11:16 PM, Leo Yan wrote: > Hi Yuanfang, > > Recently I just acrossed this part, so some comments. > > On Wed, Dec 04, 2024 at 07:23:32PM +0800, yuanfang zhang wrote: >> >> From: Yuanfang Zhang >> >> As recommended by section 4.3.7 ("Synchronization when using system >> instructions to progrom the trace unit") of ARM IHI 0064H.b, the >> self-hosted trace analyzer must perform a Context synchronization >> event between writing to the TRCPRGCTLR and reading the TRCSTATR. >> >> Fixes: ebddaad09e10 ("coresight: etm4x: Add missing single-shot control API to sysfs") >> Signed-off-by: Yuanfang Zhang >> --- >> Change in V2: >> Added comments in the code. >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 66d44a404ad0..decb3a87e27e 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -906,6 +906,13 @@ static void etm4_disable_hw(void *info) >> tsb_csync(); >> etm4x_relaxed_write32(csa, control, TRCPRGCTLR); >> >> + /* >> + * As recommended by section 4.3.7 ("Synchronization when using system >> + * instructions to progrom the trace unit") of ARM IHI 0064H.b, the >> + * self-hosted trace analyzer must perform a Context synchronization >> + * event between writing to the TRCPRGCTLR and reading the TRCSTATR. >> + */ >> + isb(); > > As described in the doc, the "isb" is only required for system > instructions case. It is good to only apply the ISB on system > register case: > > if (!csa->io_mem) > isb(); > updated in PATCH V3. >> /* wait for TRCSTATR.PMSTABLE to go to '1' */ >> if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) >> dev_err(etm_dev, > > As mentioned in system register case: "Arm recommends that the > self-hosted trace analyzer always executes an ISB instruction after > programming the trace unit registers, to ensure that all updates are > committed to the trace unit before normal code execution resumes." > > And for MMIO case: > > "When the memory is marked as Device-nGnRE or stronger. > ... > - Poll TRCSTATR to ensure the previous write has completed. > — Execute an ISB operation." > > Thus we need to add an ISB after polling. > > isb(); > updated in PATCH V3. > For consistent behaviour, a relevant thing is the dsb(sy) in > etm4_enable_hw(). I do not think the dsb(sy) is necessary, as the > driver uses the sequence "write TRCPRGCTLR + polling TRCSTATR" to > ensure the data has been populated to trace unit, the polling > operations somehow act as a read back. And the ETM manual does not > mention the requirement for DSB when enabling trace unit. Thus, we > should remove dsb(sy) (maybe use a separte patch). > updated in PATCH V3. > Mike / Suzuki / James, please confirm if my conclusions are valid. > > Thanks, > Leo