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Wed, 30 Oct 2024 17:58:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49UHwiLq032079 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 17:58:44 GMT Received: from [10.216.35.255] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 10:58:39 -0700 Message-ID: <1eaa1fc6-721c-46fd-bcc8-9b575d083dea@quicinc.com> Date: Wed, 30 Oct 2024 23:28:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/11] clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Ajit Pandey , Imran Shaik , "Jagadeesh Kona" , Stephen Boyd , , , , , References: <20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com> <20241019-qcs615-mm-clockcontroller-v1-6-4cfb96d779ae@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ptSG9c7ZCnY463oVvu7ibpeg_0jTBYJ5 X-Proofpoint-ORIG-GUID: ptSG9c7ZCnY463oVvu7ibpeg_0jTBYJ5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 mlxlogscore=924 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300141 On 10/19/2024 1:55 AM, Dmitry Baryshkov wrote: >> #include "common.h" >> +#include "gdsc.h" >> +#include "reset.h" >> + >> +enum { >> + DT_BI_TCXO, >> + DT_GPLL0, >> + DT_DSI0_PHY_PLL_OUT_BYTECLK, >> + DT_DSI0_PHY_PLL_OUT_DSICLK, >> + DT_DSI1_PHY_PLL_OUT_DSICLK, > Is there a DSI 1 PLL on this platform? As per the design of the clock controller it has a DSI1 port. -- Thanks & Regards, Taniya Das.