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Fri, 31 Jul 2026 17:57:09 +0000 (GMT) Received: from [9.124.209.55] (unknown [9.124.209.55]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 31 Jul 2026 17:57:08 +0000 (GMT) Message-ID: <1eab63fc-b70d-41ef-b720-8ae77d8e56d8@linux.ibm.com> Date: Fri, 31 Jul 2026 23:27:06 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/1] powerpc: enable dynamic preemption To: Jirka Hladky Cc: "Christophe Leroy (CS GROUP)" , paulmck@kernel.org, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, npiggin@gmail.com, bigeasy@linutronix.de, will@kernel.org, linux-kernel@vger.kernel.org References: <500d8e8c-088c-4e6d-ab53-868ade6b0eda@paulmck-laptop> <29a407ab-268e-4443-96dc-8f5f933cb63c@linux.ibm.com> <529b8d9f-54a0-4ec2-9886-83cd528e5e04@paulmck-laptop> <57d9de4a-65aa-44cf-9024-de4e5bdd1971@linux.ibm.com> <972db4f1-406b-477b-895e-59ffc643e384@kernel.org> <4be922b5-7dc2-48c1-938c-de02245bc5e2@linux.ibm.com> Content-Language: en-US From: Shrikanth Hegde In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDEzNiBTYWx0ZWRfX6Ch+w55QOPJK 36A+8CGVav9NwE4v4fCy9Ooo9PIgGt/6+o8KhY0yVUp2JAl+dMBjpuSzCts4B7QrSbH19VxJLr1 A97tbZbnfYRgHOrnPRGKu1590SdGHyU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDEzNiBTYWx0ZWRfX3sZv9aGuqCNb jVhcN+59yGz6SgBsGIPeL9sRyxGm00vTWmAqVDPMjTDvJqI1Nbf0Dp6cA+7kYYRf4hgndaaaMVl kic5e6uXtPf5jEHL75LCLYOw+DK1L3kCBFI80kMu4ljRkOah2iEaPjRFmy0sRVwi1r+EcUylIh/ unukaMVh/IaJJg8myu6FnSfTorr/wHPB4o8kleH1JtyQHYwztJmiMa5vuJmP8mH1427DBGPQluP ihytpwI2VMZxIGNSk4eht98lg/sui526Cn5f+L2P1jF1NpI09M/IsN6orF9jkAxSgJSN7RcN36j O1Pe+eThlvAce4b+E45g9caiLw7gbJDzfi8LLps8jTZriZWTwHWuvls4mNPhMvjZb/LxzBsvhqX lezh07nBGQkWZ8iehu5qY4rxuDyHE22UdAdOE58PFA06rrXrBfa17MOnR0wZBEULe74gVJoucnV XJ5IzmmlgbpMQM2RUWA== X-Authority-Analysis: v=2.4 cv=b5WCJNGx c=1 sm=1 tr=0 ts=6a6ce1fa cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=mal8egYMvLHp7vc5aikA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: hG2IEA05qLzghVrZFTxYUMPqdXkH9gsv X-Proofpoint-ORIG-GUID: 2pSQfoAUXyn4C2t1M9pezscMOXB7tMae X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310136 Hi Jirka. On 7/31/26 7:20 PM, Jirka Hladky wrote: > On Fri, Jul 31, 2026 at 10:03 AM Shrikanth Hegde wrote: >> Coming into numbers, I did notice later, arm64 numbers are almost 20x less. >> But if we compare the time taken for each operations, it tells a >> different story. > > The bottom line: PREEMPT_DYNAMIC/preempt_count overhead is present > on both RISC architectures but its visibility depends heavily on the > workload profile and hardware topology. > >> PS: I tried porting some of those changes in arm64 to powerpc to >> split preempt count into two. but i don;t see much improvement >> there. I tried moving to PACA plus splitting 64 bit into need_resched and preempt count. But it doesn;t move the needle. But it maybe worth pursuing, since it could help preemption modes. It needs more work and needs numbers across benchmark. > > Thanks for trying. Paul questioned whether barriers are actually > needed for preempt_count, or whether software interrupt disabling > would suffice (his words: "I can see why the preempt_count() > operations need to be interrupt-safe, but I don't see why you would > need barriers"). Any thoughts on whether that's feasible for > powerpc? > Barrier are likely not the concern as it is mostly nop. Also, soft disabling interrupts needs to arch specific hooks to setup before preempt_disable and replay interrupts after preempt_enable. I don't think it would benefit since interrupt disabling during this likely shouldn't happen. Maybe I don't understand how that could work.