From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8AE0C43613 for ; Thu, 20 Jun 2019 07:24:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A14982084B for ; Thu, 20 Jun 2019 07:24:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vrU7djtQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726652AbfFTHYG (ORCPT ); Thu, 20 Jun 2019 03:24:06 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54338 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725875AbfFTHYF (ORCPT ); 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Thu, 20 Jun 2019 02:23:48 -0500 Received: from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x5K7Nfrn091447; Thu, 20 Jun 2019 02:23:42 -0500 Subject: Re: [PATCH V10 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block To: Vidya Sagar , , , , , , , , , , CC: , , , , , , , , , References: <20190612095339.20118-1-vidyas@nvidia.com> <20190612095339.20118-11-vidyas@nvidia.com> From: Kishon Vijay Abraham I Message-ID: <1ecf61d7-5535-4f07-5e1e-5d492f4194da@ti.com> Date: Thu, 20 Jun 2019 12:52:16 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190612095339.20118-11-vidyas@nvidia.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/06/19 3:23 PM, Vidya Sagar wrote: > Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue > module instantiated one for each PCIe lane between Synopsys DesignWare core > based PCIe IP and Universal PHY block. > > Signed-off-by: Vidya Sagar > Reviewed-by: Rob Herring > Acked-by: Thierry Reding Acked-by: Kishon Vijay Abraham I > --- > Changes since [v9]: > * None > > Changes since [v8]: > * None > > Changes since [v7]: > * None > > Changes since [v6]: > * None > > Changes since [v5]: > * Added Sob > * Changed node name from "p2u@xxxxxxxx" to "phy@xxxxxxxx" > > Changes since [v4]: > * None > > Changes since [v3]: > * None > > Changes since [v2]: > * Changed node label to reflect new format that includes either 'hsio' or > 'nvhs' in its name to reflect which UPHY brick they belong to > > Changes since [v1]: > * This is a new patch in v2 series > > .../bindings/phy/phy-tegra194-p2u.txt | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt > new file mode 100644 > index 000000000000..d23ff90baad5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt > @@ -0,0 +1,28 @@ > +NVIDIA Tegra194 P2U binding > + > +Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High > +Speed) each interfacing with 12 and 8 P2U instances respectively. > +A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE > +interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe > +lane. > + > +Required properties: > +- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". > +- reg: Should be the physical address space and length of respective each P2U > + instance. > +- reg-names: Must include the entry "ctl". > + > +Required properties for PHY port node: > +- #phy-cells: Defined by generic PHY bindings. Must be 0. > + > +Refer to phy/phy-bindings.txt for the generic PHY binding properties. > + > +Example: > + > +p2u_hsio_0: phy@3e10000 { > + compatible = "nvidia,tegra194-p2u"; > + reg = <0x03e10000 0x10000>; > + reg-names = "ctl"; > + > + #phy-cells = <0>; > +}; >