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From: "Zhijian Li (Fujitsu)" <lizhijian@fujitsu.com>
To: Ira Weiny <ira.weiny@intel.com>,
	"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] cxl/acpi: Verify CHBS length for CXL2.0
Date: Thu, 27 Mar 2025 07:44:23 +0000	[thread overview]
Message-ID: <1ed912df-42c7-4319-8765-3167963df7b3@fujitsu.com> (raw)
In-Reply-To: <67e4c9aaedd08_138d3294ca@iweiny-mobl.notmuch>



On 27/03/2025 11:44, Ira Weiny wrote:
> Li Zhijian wrote:
>> Per CXL Spec r3.1 Table 9-21, both CXL1.1 and CXL2.0 have defined their
>> own length, verify it to avoid an invalid CHBS
> 
> 
> I think this looks fine.  But did a platform have issues with this?  

Not really, actually, I discovered it while reviewing the code and
CXL specification.

Currently, this issue arises only when I inject an incorrect length
via QEMU environment. Our hardware does not experience this problem.


> Does this need to be backported?
I remain neutral :)

Thanks



> 
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> 
> [snip]

  reply	other threads:[~2025-03-27  7:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-26  7:44 Li Zhijian
2025-03-27  3:44 ` Ira Weiny
2025-03-27  7:44   ` Zhijian Li (Fujitsu) [this message]
2025-03-27 13:36     ` Dan Williams
2025-03-28  4:15       ` Zhijian Li (Fujitsu)
2025-04-04 13:53         ` Jonathan Cameron
2025-04-07  1:52           ` Zhijian Li (Fujitsu)
2025-04-04 22:19         ` Dan Williams
2025-04-07  2:30           ` Zhijian Li (Fujitsu)

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