From: "Moger, Babu" <babu.moger@amd.com>
To: Sean Christopherson <seanjc@google.com>,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, pbonzini@redhat.com
Cc: x86@kernel.org, hpa@zytor.com, daniel.sneddon@linux.intel.com,
jpoimboe@kernel.org, pawan.kumar.gupta@linux.intel.com,
thomas.lendacky@amd.com, perry.yuan@amd.com,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH] x86/cpufeatures: Define X86_FEATURE_PREFETCHI (AMD)
Date: Mon, 28 Apr 2025 08:54:51 -0500 [thread overview]
Message-ID: <1f056b35-d455-4e65-8063-db66ab764a08@amd.com> (raw)
In-Reply-To: <174562166515.1002335.4837189500291274188.b4-ty@google.com>
On 4/25/25 18:23, Sean Christopherson wrote:
> On Tue, 08 Apr 2025 17:57:09 -0500, Babu Moger wrote:
>> The latest AMD platform has introduced a new instruction called PREFETCHI.
>> This instruction loads a cache line from a specified memory address into
>> the indicated data or instruction cache level, based on locality reference
>> hints.
>>
>> Feature bit definition:
>> CPUID_Fn80000021_EAX [bit 20] - Indicates support for IC prefetch.
>>
>> [...]
>
> Applied to kvm-x86 misc, with a rewritten shortlog and changelog to make it super
> clear this is KVM enabling.
Sean, Thank you.
Babu Moger
prev parent reply other threads:[~2025-04-28 13:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-08 22:57 Babu Moger
2025-04-09 9:23 ` Borislav Petkov
2025-04-25 23:23 ` Sean Christopherson
2025-04-28 13:54 ` Moger, Babu [this message]
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