From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E28623EAAF for ; Fri, 6 Feb 2026 21:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770412118; cv=none; b=mHe8PzT4KqIq7CrBNMZ+hP3rNRHX0v1Vit76FM+X6vBKeTjNEL1ZfVkcnW2kR78EZY+MMWrxrWlCIAWXv/OevuVhpe6LJACtHRF//FB9QJTXvYE+IH/6oesW4ybVFp9UKnVPst8Gl3ti4tKbFS+R0kiqld/pmd01dMqmZAD5HCs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770412118; c=relaxed/simple; bh=jN10LHpelzdpGpfIJCqRyRCCkUggLjf16hbEloL4B78=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=WpqzMcsX+W0c6yFtcaFCMDmZuJZ4smhMVimbOLkYBn44y1rXMjFoAX4CC34Dl3OB0a8Bpa4RaqGjp2xUYnQmfbJB8ERd8VZNn/FkhIlkSwLCF+wuwusoEi1IkDn7zFTY4nXQhV5YCwIqzUTmzotnnzSM4AcdPlUyTa2BxArUPVQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jYEfvCHD; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jYEfvCHD" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-b8864618c99so36897166b.2 for ; Fri, 06 Feb 2026 13:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770412116; x=1771016916; darn=vger.kernel.org; h=mime-version:user-agent:content-transfer-encoding :disposition-notification-to:references:in-reply-to:date:cc:to:from :subject:message-id:from:to:cc:subject:date:message-id:reply-to; bh=/+NJOFqSVdQV18UFk9RR7F7roLWkGvtxbswC+y4nQIM=; b=jYEfvCHDepwuDbCBluSx9DI12bH6+LS02mstUv7FnVQO0tj+Nc+xBojxYuc8yow+CF 5i21WpV84QZr7G/TIeQ/WFDRlxP822M4LRGNeiTqp6wQR2hAeAmO/B/hSE5/T6rUon2R FzQlMQUDKHggyEj2hH7l9x9ZfHmVyXU6hRn/yn/NZs05O+lEnXYrCu9GjqR14wu5nss8 0EJ8iccVxos86jWryhugf37wpZF5JVy87jZCBxMXDTXfGKOsDMmvMT8KxYEx6Sq7Y9nr SoF7e4J90IetVzqIY3DCTi8RuKNO3UenGswmiGUY/Csy6NZzfErMfWuFuiHhGJZT0ywz TPQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770412116; x=1771016916; h=mime-version:user-agent:content-transfer-encoding :disposition-notification-to:references:in-reply-to:date:cc:to:from :subject:message-id:x-gm-gg:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=/+NJOFqSVdQV18UFk9RR7F7roLWkGvtxbswC+y4nQIM=; b=uVwAFgptW/BA1+8zXj94orYAND+c0irEsVqFbJWH/zCXyrDtCOif7EzsCx1MOwo/Ou FPwlIbCTjFlD422ZWiiu5PEgkghJbDcjCtBPZstw4TGnMO9vtViFT0NJohmUPqLRR19Q fxPACzysNmbw7v+s6wV6PieuhmZLMbIOzRrL0TAe1RPcdpJJbIJCHzLrnFC/NV5Vl6GP TuJORuZqgNG4TO4JSJrJUNrT1eelTzitFCEmCnyCwUVBsafiyxqFEfienj9wkzfXstyH ABAqe8nDwJl3ateOytWA3wSJYzoO72LngoXMxPj3A0ccneKwynwZLiKs/K4cxyD62mTq 5JFQ== X-Forwarded-Encrypted: i=1; AJvYcCVmKUGdZEwIawjVe76DP/+fS27VqH01NcEC9+BLwjllfi4bxI4LPeUFvHftu2+U2MWWgdloWAwyEyT4kts=@vger.kernel.org X-Gm-Message-State: AOJu0Yyp9xHjdvJk7JkkgxpdlZqQOP0DGlId/3g/ZqXmjnoJSOK3+Tdd raAo4mEvdYP+nKRqvEgN9sN3pCzVdn7dRTQeIulOI5F5JbooKXjtnM2w X-Gm-Gg: AZuq6aJgnVF5CtbAMgShzwdRE8EEDSg8vJ2rm2whxoGv8gi5pXX2ATxK4r+DNOszAM3 d6fbTUaGcEZaQRf2dMtB4K+5UQNSZ5OQMP0EQcDpsbehUkq5vjabia57FcB8/ew0cHbm8stvtmk dZVuPiZ+U8QTnKgWaQqkttrOmrxJI/jqUGB3wxw9DFnQzk/C2qs1TGAVKYSFVswZqu1qu6vjZl3 +nEIUx2cQTmvFL2Ily0nZ44b2KrrUFjKe8ryedFFEyngmC/luCickreVf+sQPOI12g32ZAQcqeU 3dOClGdhaiHbLUvkree0xqjGi+OZEC2liTMbQuqIleIFVXL2qMPLQKifjyyvXOctCFOwVp2Eblg 9RRy2MAUIj3AQvq/nJu/ojd9ghVEbccfNRnRNEWwUJM44EJzqF3jX/omwS81hDEylOMpOmADoUa kaEXDadc5g6vDO9gnWeXos3R3FqWDxfHdVIZ7n7MleT5UD1Rss4kcIIGLa2Zw9obRNMC2lBXd5x M9WqQoyWw== X-Received: by 2002:a17:906:6a0f:b0:b88:5095:b740 with SMTP id a640c23a62f3a-b8edf4ead62mr117120066b.7.1770412116127; Fri, 06 Feb 2026 13:08:36 -0800 (PST) Received: from [192.168.1.239] (87-205-5-123.static.ip.netia.com.pl. [87.205.5.123]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8eda7a3004sm113593866b.15.2026.02.06.13.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 13:08:35 -0800 (PST) Message-ID: <1f0ce7317fa941ef443c0d8c04aab00b78033cc1.camel@gmail.com> Subject: Re: [PATCH v3 19/19] drm/amd/display: Add HDMI VRR desktop mode From: Tomasz =?UTF-8?Q?Paku=C5=82a?= To: Harry Wentland , alexander.deucher@amd.com, sunpeng.li@amd.com Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, siqueira@igalia.com, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, bernhard.berger@gmail.com, michel.daenzer@mailbox.org, daniel@fooishbar.org, admin@ptr1337.dev Date: Fri, 06 Feb 2026 22:08:33 +0100 In-Reply-To: References: <20260203185626.55428-1-tomasz.pakula.oficjalny@gmail.com> <20260203185626.55428-20-tomasz.pakula.oficjalny@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2026-02-06 at 13:58 -0500, Harry Wentland wrote: > On 2026-02-03 13:56, Tomasz Paku=C5=82a wrote: > > [Why] > > Many TVs and other HDMI sinks suffer from blanking and possibly other > > glitches when VRR is toggled. With FreeSync present on such sinks, they > > behave like the signal is always variable, even in fixed refresh rate > > situations. > >=20 > > [How] > > Keep HDMI VRR toggled if it's supported and not explicitly disabled. > > Additionnally, add module parameter which allows users to configure HDM= I > > VRR triggering to only happen when the signal is truly asking for > > variable state. This is useful if end user has a TV that automatically > > toggles ALLM/Game mode when VRR is active and such user doesn't want > > gaming mode in normal desktop usage. > >=20 >=20 > Can't this already be done by the compositor by simply setting the > VRR_ENABLED property on a crtc? >=20 > I don't like doing behavior behind the backs of compositors that > they might not be expecting. >=20 > Harry This actually mimics how FreeSync works on Windows. It keeps signaling VRR or well, FreeSync mode, to the sink while keeping the signal fixed.=20 Overall behavior is the same as with VRR completely disabled. Signal is only variable if the compositor sets VRR_ENABLED. It's a bit similar to freesync video or VRR_STATE_ACTIVE_FIXED. FreeSync infopacket contains separate FreeSync on Desktop, and FreeSync active fields and in this change, the check for VRR with hdmi_vrr_on_desktop is the same as for FreeSync on Desktop field. I could better show this by uploading a video to youtube, especially with a comparison to the Windows driver. Sadly, VRR_ENABLED is just a bool whereas compositors could give drivers info in three steps: Disabled, Inactive, Active. This way, we could still completely disable VRR signaling though again, the desired behavior is preset even in the Windows driver or maybe it's baked into FreeSync specification? I don't know if it's public, I know I haven't seen it but it would be nice. The need for this is due to the fact that, contrary to VESA Adaptive Sync, HDMI doesn't seem to enforce that VRR mode toggling shouldn't cause a mode change this A LOT of TVs will blank. This is especially egregious with Windows' Dynamic Refresh rate setting where the desktop becomes absolutely unusable. With constant blanking. > > Signed-off-by: Tomasz Paku=C5=82a > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + > > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++++++++++ > > .../amd/display/modules/info_packet/info_packet.c | 9 +++++++-- > > 3 files changed, 21 insertions(+), 2 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/= amdgpu/amdgpu.h > > index 312aa32064d5..d49cd55e0f35 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > @@ -269,6 +269,7 @@ extern int amdgpu_rebar; > > extern int amdgpu_wbrf; > > extern int amdgpu_user_queue; > > extern uint amdgpu_allm_mode; > > +extern bool amdgpu_hdmi_vrr_desktop_mode; > > =20 > > extern uint amdgpu_hdmi_hpd_debounce_delay_ms; > > =20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_drv.c > > index 4b038c8bbf9f..f53c2ffeffa2 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > > @@ -249,6 +249,7 @@ int amdgpu_rebar =3D -1; /* auto */ > > int amdgpu_user_queue =3D -1; > > uint amdgpu_hdmi_hpd_debounce_delay_ms; > > uint amdgpu_allm_mode =3D 1; > > +bool amdgpu_hdmi_vrr_desktop_mode =3D true; > > =20 > > DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS= , 0, > > "DRM_UT_CORE", > > @@ -1146,6 +1147,18 @@ module_param_named(hdmi_hpd_debounce_delay_ms, a= mdgpu_hdmi_hpd_debounce_delay_ms > > MODULE_PARM_DESC(allm_mode, "Changes ALLM trigger mode (0 =3D disable,= 1 =3D enable (default), 2 =3D force enable)"); > > module_param_named(allm_mode, amdgpu_allm_mode, uint, 0644); > > =20 > > +/** > > + * DOC: hdmi_vrr_on_dekstop (bool) > > + * Enables FreeSync behavior mimicking by keeping HDMI VRR signalling = active in > > + * fixed refresh rate conditions like normal desktop work/web browsing= . > > + * Possible values: > > + * > > + * - false =3D HDMI VRR is only enabled if refresh rate is truly varia= ble > > + * - true =3D Mimics FreeSync behavior and keeps HDMI VRR always acti= ve > > + */ > > +MODULE_PARM_DESC(hdmi_vrr_desktop_mode, "Changes HDMI VRR desktop mode= (false =3D disable, true =3D enable (default))"); > > +module_param_named(hdmi_vrr_desktop_mode, amdgpu_hdmi_vrr_desktop_mode= , bool, 0644); > > + > > /* These devices are not supported by amdgpu. > > * They are supported by the mach64, r128, radeon drivers > > */ > > diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packe= t.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c > > index 5fd9e8aadc98..b41e2240e1ae 100644 > > --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c > > +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c > > @@ -654,8 +654,13 @@ static void build_vtem_infopacket_data(const struc= t dc_stream_state *stream, > > bool vrr_active =3D false; > > bool rb =3D false; > > =20 > > - vrr_active =3D vrr->state =3D=3D VRR_STATE_ACTIVE_VARIABLE || > > - vrr->state =3D=3D VRR_STATE_ACTIVE_FIXED; > > + if (amdgpu_hdmi_vrr_desktop_mode) { > > + vrr_active =3D vrr->state !=3D VRR_STATE_UNSUPPORTED && > > + vrr->state !=3D VRR_STATE_DISABLED; > > + } else { > > + vrr_active =3D vrr->state =3D=3D VRR_STATE_ACTIVE_VARIABLE || > > + vrr->state =3D=3D VRR_STATE_ACTIVE_FIXED; > > + } > > =20 > > infopacket->sb[VTEM_MD0] =3D VTEM_M_CONST << VTEM_M_CONST_BIT; > > infopacket->sb[VTEM_MD0] |=3D VTEM_FVA_FACTOR << VTEM_FVA_BIT;