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Tue, 12 Mar 2019 12:05:48 -0500 Received: from [172.24.190.89] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2CH5ibf009486; Tue, 12 Mar 2019 12:05:44 -0500 Subject: Re: [RFC PATCH 2/2] spi: spi-mem: Add support for Zynq QSPI controller To: Naga Sureshkumar Relli , "broonie@kernel.org" , "bbrezillon@kernel.org" CC: "linux-spi@vger.kernel.org" , "dwmw2@infradead.org" , "marek.vasut@gmail.com" , "richard@nod.at" , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Michal Simek , "nagasuresh12@gmail.com" References: <1551337361-11665-1-git-send-email-naga.sureshkumar.relli@xilinx.com> <48dafcc4-1b9d-9ce2-9228-78e73252781f@ti.com> <602dd5ed-48b6-2098-fc2a-e36192b6a8e7@ti.com> From: Vignesh Raghavendra Message-ID: <1f4df1cc-7a2f-1601-0553-1db5d69b492d@ti.com> Date: Tue, 12 Mar 2019 22:36:43 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 11/03/19 10:02 AM, Naga Sureshkumar Relli wrote: > Hi Vignesh, > >> -----Original Message----- >> From: linux-spi-owner@vger.kernel.org On Behalf Of >> Vignesh Raghavendra >> Sent: Friday, March 8, 2019 10:20 AM >> To: Naga Sureshkumar Relli ; broonie@kernel.org; >> bbrezillon@kernel.org >> Cc: linux-spi@vger.kernel.org; dwmw2@infradead.org; marek.vasut@gmail.com; >> richard@nod.at; linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org; Michal Simek >> ; nagasuresh12@gmail.com >> Subject: Re: [RFC PATCH 2/2] spi: spi-mem: Add support for Zynq QSPI controller >> >> >> >> On 01/03/19 4:32 PM, Naga Sureshkumar Relli wrote: >>>>> +static bool zynq_qspi_supports_op(struct spi_mem *mem, >>>>> + const struct spi_mem_op *op) >>>>> +{ >>>>> + int ret; >>>>> + >>>>> + ret = zynq_qspi_check_buswidth(op->cmd.buswidth); >>>>> + >>>>> + if (op->addr.nbytes) >>>>> + ret |= zynq_qspi_check_buswidth(op->addr.buswidth); >>>>> + >>>>> + if (op->dummy.nbytes) >>>>> + ret |= zynq_qspi_check_buswidth(op->dummy.buswidth); >>>>> + >>>>> + if (op->data.nbytes) >>>>> + ret |= zynq_qspi_check_buswidth(op->data.buswidth); >>>>> + >>>>> + if (ret) >>>>> + return false; >>>>> + >>>> spi_mem_default_supports_op() already has this code. >>>> Could you change, spi_mem_supports_op() to call >>>> spi_mem_default_supports_op() first before controller specific >>>> ->supports_op()? So that, above code can be dropped. >>> Ok, I will update it. >>>>> + /* >>>>> + * The number of address bytes should be equal to or less than 3 bytes. >>>>> + */ >>>>> + if (op->addr.nbytes > 3) >>>>> + return false; >>>>> + >>>> Hmm, how does the driver handle flash devices >16MB in size? Not supported? >>> Zynq QSPI controller doesn't support 4 byte addressing. >>> So to support > 16MB size, we have to use EAR(extended address register). >>> As it is initial version of driver, I haven't added this code. This needs to be added in spi-nor.c. >>> Previously I have sent an RFC patch to support all these. >>> But Boris suggested to upstream the basic one first under spi-mem frame work. >>> Not only this support, there are other features like dual parallel and dual stacked. >>> All these features require additional support from spi-nor framework. >>> We have another QSPI controller on ZynqMP SOC, which is also similar(but it supports >> 4Byte addressing). >>> So by consolidating all these, I sent this patch. >>> >>> Please let me know your suggestion on this. >> >> Sounds fine to me. Support for > 16MB flash using EAR can come later. > Thanks. > Shall I wait for others to review or go ahead by addressing your previous comments? > Typically, for a new driver, I would wait at least 2 weeks from date of posting so that other reviewers have sufficient time to look into the patch. -- Regards Vignesh