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[73.228.159.35]) by smtp.googlemail.com with ESMTPSA id 586e51a60fabf-29f93552d34sm590951fac.24.2024.12.07.08.50.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 07 Dec 2024 08:50:03 -0800 (PST) Message-ID: <1f597801-62b7-4fb1-9ffe-1b9554c4e23c@ieee.org> Date: Sat, 7 Dec 2024 10:50:01 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] soc: hisilicon: Add power control support for kunpeng HBM To: Zhang Zekun , xuwei5@hisilicon.com, lihuisong@huawei.com, Jonathan.Cameron@huawei.com Cc: linux-kernel@vger.kernel.org, liuyongqiang13@huawei.com References: <20241206112812.32618-1-zhangzekun11@huawei.com> Content-Language: en-US From: Alex Elder In-Reply-To: <20241206112812.32618-1-zhangzekun11@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/6/24 5:28 AM, Zhang Zekun wrote: > Add power control support for High Bandwidth Memory (HBM) for Kunpeng SoC > platform. HBM devices on Kunpeng SoC can provide higher bandwidth at the > cost of higher power consumption. Providing power control methods can help > reducing the power when the workload does not need use HBM. Could you explain a little more here how HBM is represented in the system? When it's powered on, it seems like it's "just memory". And what you're doing here is enabling a power optimization to allow this type of memory to be powered off when not in use. How do you know whether it is in use? What entity is meant to be able to power this memory on and off? In addition, it looks like there can be more than one instance of an HBM device, and each is available to be used only for certain CPUs. Can you provide more information about that sort of architectural detail? Finally, the second patch enables "cache" functionality. Maybe this is something defined by ACPI and is well understood by others but it's not clear to me what this even means. How is an HBM used, and how does its cache enabled/disabled state interact with the device enabled/disabled state? Is an HBM device something completely different from an HBM cache device? I guess I just lack a big-picture overview of how this HBM fits into a system. -Alex > > Zhang Zekun (2): > soc: hisilicon: kunpeng_hbmdev: Add support for controling the power > of hbm memory > soc: hisilicon: kunpeng_hbmcache: Add support for online and offline > the hbm cache > > MAINTAINERS | 7 + > drivers/soc/hisilicon/Kconfig | 23 +++ > drivers/soc/hisilicon/Makefile | 2 + > drivers/soc/hisilicon/kunpeng_hbm.h | 31 ++++ > drivers/soc/hisilicon/kunpeng_hbmcache.c | 136 +++++++++++++++ > drivers/soc/hisilicon/kunpeng_hbmdev.c | 210 +++++++++++++++++++++++ > 6 files changed, 409 insertions(+) > create mode 100644 drivers/soc/hisilicon/kunpeng_hbm.h > create mode 100644 drivers/soc/hisilicon/kunpeng_hbmcache.c > create mode 100644 drivers/soc/hisilicon/kunpeng_hbmdev.c >