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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af635a63116sm577931366b.90.2025.07.29.04.17.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Jul 2025 04:17:42 -0700 (PDT) Message-ID: <1f6fc7ce-5826-4f59-89d7-ac691a3ae785@oss.qualcomm.com> Date: Tue, 29 Jul 2025 13:17:39 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/2] arm64: dts: qcom: Add display support for QCS615 To: Fange Zhang , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xiangxu Yin , Li Liu , Dmitry Baryshkov References: <20250718-add-display-support-for-qcs615-platform-v5-0-8579788ea195@oss.qualcomm.com> <20250718-add-display-support-for-qcs615-platform-v5-1-8579788ea195@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250718-add-display-support-for-qcs615-platform-v5-1-8579788ea195@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: AmRviw_E6_XGUcS-KPeeWSpXrVE9AfUA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI5MDA4NyBTYWx0ZWRfX/poTD4qFHEDK pXG5Usi5fU4sTTwLgwlrJH4y1TZaxtz+2JGPrO3Z1VeKFTSPWmu0JTm1uYGI8jXmFlqOU9x/wSt eaAgEYnnWCZ+ZOdGCrse3TCXf3vyMGp9NWN8rlFZXsdOuI2tZ/Gb0PoZaDa7j3fJP2th+1aR6cK n2+eei9oooBPxDNv6LGEVib6BwMfYbRLcayRUqazI1+h0OykbS6mZ3kOLxkpWywM0rLJcoFz2d7 fG8Ndb+PlT2OEGUXUHF3FuV5GwECXlBG9q8XeQLlt8Oyr8nJsKUrg8zk43ZWHEVt7taDX75ca1U hfnayUvRBXNz2Qio4avQ3wKZXbkmR7WSTPaJT3TJmZKDv7nt+bCKem9p7v6PSs/x3isy5rXmbnP oM70RmlnIxK9Qy38MF9WL/GytpdRiHLqD/VaZ4kR9jWCuC7gujxfXqLUi4wliNV5A0Pufx0f X-Proofpoint-GUID: AmRviw_E6_XGUcS-KPeeWSpXrVE9AfUA X-Authority-Analysis: v=2.4 cv=KtNN2XWN c=1 sm=1 tr=0 ts=6888add9 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Frto0rYOkVf98Gw2rTwA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-29_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507290087 On 7/18/25 2:56 PM, Fange Zhang wrote: > From: Li Liu > > Add display MDSS and DSI configuration for QCS615 platform. > QCS615 has a DP port, and DP support will be added in a later patch. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Li Liu > Signed-off-by: Fange Zhang > --- [...] > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm6150-dpu"; > + reg = <0x0 0x0ae01000 0x0 0x8f000>, > + <0x0 0x0aeb0000 0x0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "core", "vsync"; 1 per line please, everywhere> + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; Is this necessary? > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_CX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; interrupts-extended > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; Please keep a \n between properties and subnodes > + dpu_intf0_out: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-19200000 { > + opp-hz = /bits/ 64 <19200000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-25600000 { > + opp-hz = /bits/ 64 <25600000>; > + required-opps = <&rpmhpd_opp_svs>; This and the above frequency are missing one zero (i.e. you have a 10x underclock) [...] > + mdss_dsi0_phy: phy@ae94400 { > + compatible = "qcom,sm6150-dsi-phy-14nm"; > + reg = <0x0 0x0ae94400 0x0 0x100>, > + <0x0 0x0ae94500 0x0 0x300>, > + <0x0 0x0ae94800 0x0 0x188>; sz = 0x124 > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,qcs615-dispcc"; > reg = <0 0x0af00000 0 0x20000>; > > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, > + <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>, #include Konrad