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Fri, 9 Aug 2024 14:43:38 +0800 Received: from RTEXMBS02.realtek.com.tw (172.21.6.95) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 9 Aug 2024 14:43:39 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXMBS02.realtek.com.tw (172.21.6.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 9 Aug 2024 14:43:39 +0800 Received: from RTEXMBS04.realtek.com.tw ([fe80::1a1:9ae3:e313:52e7]) by RTEXMBS04.realtek.com.tw ([fe80::1a1:9ae3:e313:52e7%5]) with mapi id 15.01.2507.035; Fri, 9 Aug 2024 14:43:39 +0800 From: Justin Lai To: Jakub Kicinski CC: "davem@davemloft.net" , "edumazet@google.com" , "pabeni@redhat.com" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" , "andrew@lunn.ch" , "jiri@resnulli.us" , "horms@kernel.org" , "rkannoth@marvell.com" , "jdamato@fastly.com" , Ping-Ke Shih , Larry Chiu Subject: RE: [PATCH net-next v26 07/13] rtase: Implement a function to receive packets Thread-Topic: [PATCH net-next v26 07/13] rtase: Implement a function to receive packets Thread-Index: AQHa6HuwwZ+4plTmsUmDtMJWq0tmxbIdu1mAgADBvuA= Date: Fri, 9 Aug 2024 06:43:38 +0000 Message-ID: <1f846891e9264b94bf00cb934dd83d2a@realtek.com> References: <20240807033723.485207-1-justinlai0215@realtek.com> <20240807033723.485207-8-justinlai0215@realtek.com> <20240808200705.0e77147c@kernel.org> In-Reply-To: <20240808200705.0e77147c@kernel.org> Accept-Language: zh-TW, en-US Content-Language: zh-TW x-kse-serverinfo: RTEXMBS02.realtek.com.tw, 9 x-kse-antispam-interceptor-info: fallback x-kse-antivirus-interceptor-info: fallback Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-KSE-AntiSpam-Interceptor-Info: fallback > On Wed, 7 Aug 2024 11:37:17 +0800 Justin Lai wrote: > > +static int rx_handler(struct rtase_ring *ring, int budget) { > > + union rtase_rx_desc *desc_base =3D ring->desc; > > + u32 pkt_size, cur_rx, delta, entry, status; > > + struct rtase_private *tp =3D ring->ivec->tp; > > + struct net_device *dev =3D tp->dev; > > + union rtase_rx_desc *desc; > > + struct sk_buff *skb; > > + int workdone =3D 0; > > + > > + cur_rx =3D ring->cur_idx; > > + entry =3D cur_rx % RTASE_NUM_DESC; > > + desc =3D &desc_base[entry]; > > + > > + do { > > + /* make sure discriptor has been updated */ > > + dma_rmb(); >=20 > I think I already asked, but this still makes no sense to me. > dma barriers are between accesses to descriptors. > dma_rmb() ensures ordering of two reads. > Because modern CPUs can perform reads out of order. > What two reads is this barrier ordering? >=20 > Please read the doc on memory barriers relating to dma. > I think this is in the wrong place. >=20 > r8169 gets it right. Thank you for your reply. I will modify it. Thanks Justin >=20 > > + status =3D le32_to_cpu(desc->desc_status.opts1); > > + > > + if (status & RTASE_DESC_OWN) > > + break; > > +