From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64E56254861 for ; Fri, 28 Feb 2025 16:38:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740760709; cv=none; b=RYjAzbJd9q2P79eZT4VK+cuizexBsDQeUoFe/Vl13ICaO5cDsD0LW1HeDD/8hcI2UpOVyZhiE60KAHa1aOWk6mN6SuCihcV5YELglRApsoxUNwwcrIg6k9Mf49GxxnBFcnn5XWqVpIavNm3o+BcVpEotPHMVJH97Ns/zwclVDOw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740760709; c=relaxed/simple; bh=QErM3wHjLyAkdDm7rcn/oamG2MYpwbwyh/uwrbQVH+Y=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=AKiHqPQo1+RgKoihGhfltrnOweExC26luygHvaq5/AEr6WxppZN3uUnLc8F2PttA2e5QsS4lf2Z8bYpqBTvJYaoUXxYwVt2+z998TyppVh3hHS0NXvlJWz7skzqZerccHP4jS0xJ/KLvmHpt9WDg5cS49fQsf9IL3V95mvFjDj8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1to3NI-0004MW-V4; Fri, 28 Feb 2025 17:38:08 +0100 Received: from lupine.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::4e] helo=lupine) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1to3NH-003KIL-36; Fri, 28 Feb 2025 17:38:07 +0100 Received: from pza by lupine with local (Exim 4.96) (envelope-from ) id 1to3NH-000D1T-2r; Fri, 28 Feb 2025 17:38:07 +0100 Message-ID: <1fcf08fe37a8e14c4acae445d65bd1503b13b6d2.camel@pengutronix.de> Subject: Re: [PATCH 3/4] media: platform: qcom/iris: add support for vpu33 From: Philipp Zabel To: Neil Armstrong , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 28 Feb 2025 17:38:07 +0100 In-Reply-To: <20250225-topic-sm8x50-iris-v10-v1-3-128ef05d9665@linaro.org> References: <20250225-topic-sm8x50-iris-v10-v1-0-128ef05d9665@linaro.org> <20250225-topic-sm8x50-iris-v10-v1-3-128ef05d9665@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org On Di, 2025-02-25 at 10:05 +0100, Neil Armstrong wrote: > The IRIS acceleration found in the SM8650 platforms uses the vpu33 > hardware version, and requires a slighly different reset and power off > sequences in order to properly get out of runtime suspend. >=20 > Signed-off-by: Neil Armstrong > --- > drivers/media/platform/qcom/iris/Makefile | 1 + > drivers/media/platform/qcom/iris/iris_vpu33.c | 315 +++++++++++++++= ++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > 3 files changed, 317 insertions(+) >=20 > diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/pl= atform/qcom/iris/Makefile > index 35390534534e93f4617c1036a05ca0921567ba1d..6b64c9988505afd9707c70444= 9d60bb53209229f 100644 > --- a/drivers/media/platform/qcom/iris/Makefile > +++ b/drivers/media/platform/qcom/iris/Makefile > @@ -21,6 +21,7 @@ qcom-iris-objs +=3D \ > iris_vdec.o \ > iris_vpu2.o \ > iris_vpu3.o \ > + iris_vpu33.o \ > iris_vpu_buffer.o \ > iris_vpu_common.o \ > =20 > diff --git a/drivers/media/platform/qcom/iris/iris_vpu33.c b/drivers/medi= a/platform/qcom/iris/iris_vpu33.c > new file mode 100644 > index 0000000000000000000000000000000000000000..128a050f206f99ec0d43b97ff= 995fa50d5684150 > --- /dev/null > +++ b/drivers/media/platform/qcom/iris/iris_vpu33.c > @@ -0,0 +1,315 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights r= eserved. > + */ > + > +#include > +#include > + > +#include "iris_instance.h" > +#include "iris_vpu_common.h" > +#include "iris_vpu_register_defines.h" > + > +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > +#define AON_BASE_OFFS 0x000E0000 > +#define AON_MVP_NOC_RESET 0x0001F000 > + > +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > +#define REQ_POWER_DOWN_PREP BIT(0) > +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > +#define CORE_CLK_RUN 0x0 > + > +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > +#define CTL_AXI_CLK_HALT BIT(0) > +#define CTL_CLK_HALT BIT(1) > + > +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > +#define RESET_HIGH BIT(0) > + > +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) > +#define CORE_BRIDGE_SW_RESET BIT(0) > +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) > + > +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > +#define MSK_CORE_POWER_ON BIT(1) > + > +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) > +#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) > + > +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) > + > +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) > + > +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > + > +#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) > +#define SW_RESET BIT(0) > +#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) > +#define NOC_HALT BIT(0) > +#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) > + > +#define VCODEC_DMA_SPARE_3 0x87B8 > + > +static int reset_control_bulk_assert_id(int num_rstcs, > + struct reset_control_bulk_data *rstcs, > + char *id) > +{ > + int i; > + > + for (i =3D 0; i < num_rstcs; ++i) { > + if (!strcmp(rstcs[i].id, id)) > + return reset_control_assert(rstcs[i].rstc); > + } > + > + return -ENODEV; > +} > + > +static int reset_control_bulk_deassert_id(int num_rstcs, > + struct reset_control_bulk_data *rstcs, > + char *id) > +{ > + int i; > + > + for (i =3D 0; i < num_rstcs; ++i) { > + if (!strcmp(rstcs[i].id, id)) > + return reset_control_deassert(rstcs[i].rstc); > + } > + > + return -ENODEV; > +} Please adapt the abstractions instead of working around them. If the driver isn't suited for a single reset_control_bulk_data in iris_core, split it into multiple groups, or store the resets individually. At the very least, this could use constant indices instead of linear search with string compares. regards Philipp