From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE06B3812D2; Mon, 25 May 2026 12:22:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779711778; cv=none; b=ImF/2qR5sqTqLQkQuBTeYn81qA+pHqw4sR4RgqwWeQqJf0yEqFsacxW9DaW05sHhU7aGsa+7EQjcDJDYBiHTaPRHFi0ev6BMp6edmuHejv6014dpbDPJxoSRtbOXbQBOwaJMw2wtICG5Ps50pYrUB0QUDD0HNRmXQbUFOOU9OTQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779711778; c=relaxed/simple; bh=7cta4UESMkPob+xTSBhcOLsucZ7b+POlZ3aTECK9ytA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=i5ieFvhTmRAKes49Lc96YUmKvgWkphCjmkhGPYBpZgHFizbne9uy1WS9qN5lANnx9mDweHnhBKBhHUlcsQ3ZU4HIPqbSxzX6aFIinNio/vCSbnUa2js4yeumCBnQ3CEmNZA62GQAeD2wniO6LjmTqKLHApn8HpSPFGJDjW3JvIU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DjBAJDL8; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DjBAJDL8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1DA3B1F000E9; Mon, 25 May 2026 12:22:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779711776; bh=UPgmERJ8/sRCOwwVj/MiRxzf5Ss7A55xUqwU6ZnpZww=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=DjBAJDL8t7olMZy/s+nmuNkNX0nrWNqGakwSqSzvm+njYJPJf2Eqz/TjLuVpe37wy kzujRhkMx0jgP+nDrVI8d3NOBzQcNDknuzSNFRpcjQaSV7WgLSpbkucAzP64GBd05t QKfNCCEWZxv06dCSi1FFRO0mH1WQ2Dwyn/BBlEUB8PpmsGTJGdXJ4h/LEJLX5pgNKg ktWBuI/Zb4/D86r+LN/tvI6OXQug7Aj3TREtxrV38MXJvem6DsXa+3SDgj19KT3GOo 1i0mPMnN3OVhKHDqTDrqQyVDUn3ZJmRSoqB5d60f6jLEH6PcLHxXDKqBsurAVRwR8j aQSXCFES1DqPQ== Message-ID: <1fcfe6d0-f0c9-4041-8c29-d408f4cde195@kernel.org> Date: Mon, 25 May 2026 14:22:50 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] PCI: qcom: Add Support for Eliza To: Manivannan Sadhasivam Cc: Krishna Chaitanya Chundru , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260521-eliza-v1-0-97cdbe88389d@oss.qualcomm.com> <20260521-eliza-v1-3-97cdbe88389d@oss.qualcomm.com> <20260522-discerning-sympathetic-moth-daa9e7@quoll> <5593d136-569e-4ba9-9a2f-e635125899aa@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/05/2026 08:11, Manivannan Sadhasivam wrote: > On Fri, May 22, 2026 at 01:03:09PM +0200, Krzysztof Kozlowski wrote: >> On 22/05/2026 12:48, Manivannan Sadhasivam wrote: >>> On Fri, May 22, 2026 at 11:34:30AM +0200, Krzysztof Kozlowski wrote: >>>> On 22/05/2026 11:31, Krishna Chaitanya Chundru wrote: >>>>> >>>>> >>>>> On 5/22/2026 12:21 PM, Krzysztof Kozlowski wrote: >>>>>> On Thu, May 21, 2026 at 07:35:31PM +0530, Krishna Chaitanya Chundru wrote: >>>>>>> Add support for Eliza soc, which has two PCIe controllers capable >>>>>>> of 8GT/s X1 and 8GT/s X2, using the cfg_1_9_0 configuration. >>>>>>> >>>>>>> Signed-off-by: Krishna Chaitanya Chundru >>>>>>> --- >>>>>>> drivers/pci/controller/dwc/pcie-qcom.c | 1 + >>>>>>> 1 file changed, 1 insertion(+) >>>>>>> >>>>>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >>>>>>> index af6bf5cce65b..40f0a5f247eb 100644 >>>>>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c >>>>>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >>>>>>> @@ -2123,6 +2123,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) >>>>>>> static const struct of_device_id qcom_pcie_match[] = { >>>>>>> { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, >>>>>>> { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, >>>>>>> + { .compatible = "qcom,pcie-eliza", .data = &cfg_1_9_0 }, >>>>>> So compatible with sm8550. Why isn't this explained in commit msg of >>>>>> the binding? >>>>> No, PCIe controller is not compatible with sm8550, we are just re using the boot >>>>> sequence used by the sm8550. >>>> >>>> Then with what it is compatible? You cannot use someone else's match >>>> data and claim they are not compatible. This is contradictory to itself. >>>> >>> >>> 'cfg_1_9_0' is the match data of base PCIe IP v1.9.0, not just SM8550. The 'ops' >>> callbacks for 'cfg_1_9_0' are compatible with PCIe IPs used in many SoCs such as >>> SM8550, SM8450, SM8350, SM8250, SM8150, SDX55, SC8180X, and SC7280. And Eliza is >>> also falling into the same category. >>> >> And if all implementations uses the same SW interface, why are you >> claiming these are not compatible? >> > > I didn't 'claim' these SoCs are not compatible. In fact, I explicitly said that > Eliza is compatible with the base IP v1.9.0. But the resources such as clocks, > regulators might be different between them, though the SWI is compatible. So > Eliza deserves a new compatible. Whether Eliza deserves a new compatible was NEVER a part of discussion here. Bindings are very clear here and do not leave any room for interpretation. We discuss ONLY this patch. > > Also, the direct baseline of Eliza is not supported in upstream. So by > 'compatible', if you are referring to 'fallback' in DT, then using SM8750 would > be appropriate. You still won't get an entry for sm8750, so not sure where does that bring you... Best regards, Krzysztof