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Fri, 23 Oct 2026 05:04:02 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b432c96badsm977598a12.14.2026.10.23.05.03.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Oct 2026 05:04:01 -0700 (PDT) Message-ID: <1feb10d8-75f3-4dbf-9fae-807dc5a22c25@oss.qualcomm.com> Date: Fri, 23 Oct 2026 14:03:57 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches To: Yin Li , Ben Horgan , Rob Herring Cc: James Morse , Shanker Donthineni , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Bjorn Andersson , Konrad Dybcio , Gavin Shan , Andre Przywara , Drew Fustini , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Shaopeng Tan , trilok.soni@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, ganapatrao.kulkarni@oss.qualcomm.com, Srivathsa L Rao , Huang Yiwei , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, devicetree@vger.kernel.org References: <20261008-mpam-resctrl-dt-knp-support-v3-0-35196c2b43bf@oss.qualcomm.com> <20261008-mpam-resctrl-dt-knp-support-v3-8-35196c2b43bf@oss.qualcomm.com> <20261008210004.GA1318789-robh@kernel.org> <1d764a3d-7935-4e26-b1c2-92537e1d3811@oss.qualcomm.com> <893507ca-b956-474c-9124-92fbfc25e9ab@arm.com> <6e06228b-827a-4321-99c1-3e0e961abd61@arm.com> <86fee017-c9cb-4583-beab-4f29919fb518@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <86fee017-c9cb-4583-beab-4f29919fb518@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIzMDA0NiBTYWx0ZWRfX0FyPcTss/7Lh AI+uX5lm5FB4AVl1w5fsdh0S23znnok75XxejbqxUnsFkfuENQZ3NbD82ZxKc4UdxEwIKPpC42C MuZw1knoGcjSS35WLpiM+ATAnBgEK78= X-Proofpoint-GUID: CRoDGmxoUCtgl4DXCTf8_K0rBpQBhzXX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIzMDA0NiBTYWx0ZWRfX0ywneN6mbGQ5 0nEgTMBOTHn2wf6+4a8VsrMx88xuU7YUqi23su2UL6dmpF8aLQAlTJtZU8EJY0yXrmhO+j1+iqZ ywiPEq4RRbsIjWbDbS4j7+GP/n54S9jalvn66o+Me2ZRvFZ77ef3p36y5dBbeT3rHrhU7ISRc3L dW15XdhbTtUTmBmjBp/t4sO/LRgnMsuqE/0PPnnrBjv8J0yuPy2ISvnu930fwO2tvppg8IhcJfi b5pd2al+f5+Ze7IL0+a3hyysfEdtwH4zQQW3FtGFRQyuX9yAXFpptr2WEKa4kU9L8kIvfdFWsC5 ZkkJ1ZzzcxH/hsN2iM9sfIBbo+6v6ITskmltjDRtLPhE2ux8BIuTr8ks11jTTwaTgl9yArQPqvQ q5jS9wqlJk231Tmq9tcQs2B7H9qb/TtaMqmzg8eZ/aP7XMghVXyUHqudUBxKQMkAslfb7rm97pW cI8AifGpKGl+B+y3aRw== X-Proofpoint-ORIG-GUID: CRoDGmxoUCtgl4DXCTf8_K0rBpQBhzXX X-Authority-Analysis: v=2.4 cv=BdBNQbt2 c=1 sm=1 tr=0 ts=6adb4d34 cx=c_pps a=UbhLPJ621ZpgOD2l3yZY1w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=u5pNeYj4kXT91oPWfH4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TOPH6uDL9cOC6tEoww4z:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-23_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610230046 On 10/14/26 9:09 AM, Yin Li wrote: > > > On 10/13/2026 6:37 PM, Ben Horgan wrote: >> Hi Yin, [...] > Hi Ben, Konrad, > > The original 0x10000 reflects the per-MSC register block size as > allocated in the KNP hardware — as Konrad noted, Qualcomm DTs tend to > use "how much register space is allocated for this block" rather than > "what the last used register ends" to avoid holes. > > We'd like to update it to 0x321c to give other platform authors a more useful reference, without exposing KNP-internal details such as address holes between blocks. In our case, we don't implement MPAMCFG_MBW_PBM, and — as you noted — the registers from 0x3000 onward are domain-specific; since we have no domains, those aren't used either. So the actual footprint we need is smaller than 0x321c, but showing the full 0x321c gives other authors a complete picture of the allocated register space. > > That said, this patch is marked DNM and is intended as a local > verification example only, not for merging. If you don't intend it to get merged, you can even put 0x12345 in there. But for future submissions that will have the intent to be merged, please stick to the 0x10000 size Konrad