From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751342AbdING1M (ORCPT ); Thu, 14 Sep 2017 02:27:12 -0400 Received: from mga01.intel.com ([192.55.52.88]:43400 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751132AbdING1K (ORCPT ); Thu, 14 Sep 2017 02:27:10 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,391,1500966000"; d="scan'208";a="900119292" Subject: Re: [PATCH v1 1/5] mmc: sdhci-msm: fix issue with power irq To: Vijay Viswanath , ulf.hansson@linaro.org, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, asutoshd@codeaurora.org, stummala@codeaurora.org, riteshh@codeaurora.org, subhashj@codeaurora.org References: <1504097509-58983-1-git-send-email-vviswana@codeaurora.org> <1504097509-58983-2-git-send-email-vviswana@codeaurora.org> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <1ff495dd-cb66-f49b-ed23-6994e5ccdc0f@intel.com> Date: Thu, 14 Sep 2017 09:20:30 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1504097509-58983-2-git-send-email-vviswana@codeaurora.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/08/17 15:51, Vijay Viswanath wrote: > From: Subhash Jadavani > > SDCC controller reset (SW_RST) during probe may trigger power irq if > previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we > enable the power irq interrupt in GIC (by registering the interrupt > handler), we need to ensure that any pending power irq interrupt status > is acknowledged otherwise power irq interrupt handler would be fired > prematurely. > > Signed-off-by: Subhash Jadavani > Signed-off-by: Vijay Viswanath Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index 9d601dc..d636251 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -1250,6 +1250,21 @@ static int sdhci_msm_probe(struct platform_device *pdev) > CORE_VENDOR_SPEC_CAPABILITIES0); > } > > + /* > + * Power on reset state may trigger power irq if previous status of > + * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq > + * interrupt in GIC, any pending power irq interrupt should be > + * acknowledged. Otherwise power irq interrupt handler would be > + * fired prematurely. > + */ > + sdhci_msm_voltage_switch(host); > + > + /* > + * Ensure that above writes are propogated before interrupt enablement > + * in GIC. > + */ > + mb(); > + > /* Setup IRQ for handling power/voltage tasks with PMIC */ > msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); > if (msm_host->pwr_irq < 0) { > @@ -1259,6 +1274,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) > goto clk_disable; > } > > + /* Enable pwr irq interrupts */ > + writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK); > + > ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, > sdhci_msm_pwr_irq, IRQF_ONESHOT, > dev_name(&pdev->dev), host); >