From: Jerome Brunet <jbrunet@baylibre.com>
To: Junhui Liu <junhui.liu@pigmoral.tech>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Junhui Liu <junhui.liu@pigmoral.tech>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Brian Masney <bmasney@redhat.com>
Subject: Re: [PATCH v5 1/6] clk: correct clk_div_mask() return value for width == 32
Date: Tue, 29 Sep 2026 20:03:28 +0200 [thread overview]
Message-ID: <1j7bk43pfz.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20260514-dr1v90-cru-v5-1-34f3021aab51@pigmoral.tech>
On jeu. 14 mai 2026 at 17:27, Junhui Liu <junhui.liu@pigmoral.tech> wrote:
> The macro clk_div_mask() currently wraps to zero when width is 32 due to
> 1 << 32 being undefined behavior. This leads to incorrect mask generation
> and prevents correct retrieval of register field values for 32-bit-wide
> dividers.
>
> Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely
> on a 32-bit val entry in their div_table to match a div, so providing a
> full 32-bit mask is necessary.
>
> Fix this by using the standard GENMASK() macro. This safely resolves the
> undefined behavior on both 32-bit and 64-bit architectures, while also
> benefiting from the built-in compile-time type and bounds checking
> provided by the GENMASK() macro.
>
> Cc: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> Cc: Brian Masney <bmasney@redhat.com>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
next prev parent reply other threads:[~2026-09-29 18:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-14 9:27 [PATCH v5 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
2026-05-14 9:27 ` [PATCH v5 1/6] clk: correct clk_div_mask() return value for width == 32 Junhui Liu
2026-05-18 5:58 ` Troy Mitchell
2026-05-18 15:53 ` Brian Masney
2026-09-29 18:03 ` Jerome Brunet [this message]
2026-05-14 9:27 ` [PATCH v5 2/6] dt-bindings: clock: add Anlogic DR1V90 CRU Junhui Liu
2026-05-14 9:27 ` [PATCH v5 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC Junhui Liu
2026-05-14 9:27 ` [PATCH v5 4/6] reset: anlogic: add support for Anlogic DR1V90 resets Junhui Liu
2026-06-29 20:58 ` Brian Masney
2026-06-30 7:23 ` Philipp Zabel
2026-06-30 7:06 ` Philipp Zabel
2026-05-14 9:27 ` [PATCH v5 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 Junhui Liu
2026-05-14 9:27 ` [PATCH v5 6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry Junhui Liu
2026-09-29 18:12 ` [PATCH v5 0/6] clk/reset: anlogic: add support for DR1V90 SoC Brian Masney
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