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Wed, 08 Apr 2026 10:34:19 -0700 (PDT) From: Jerome Brunet To: Chuan Liu Cc: Krzysztof Kozlowski , Neil Armstrong , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: Re: [PATCH 04/13] clk: amlogic: Add basic clock driver In-Reply-To: <76ef272c-e09a-400e-b381-82d7f29760ca@amlogic.com> (Chuan Liu's message of "Wed, 8 Apr 2026 22:32:56 +0800") References: <20260209-a9_clock_driver-v1-0-a9198dc03d2a@amlogic.com> <20260209-a9_clock_driver-v1-4-a9198dc03d2a@amlogic.com> <89cc0724-32a8-4da5-8070-c128cafcfc82@kernel.org> <76ef272c-e09a-400e-b381-82d7f29760ca@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Wed, 08 Apr 2026 19:34:18 +0200 Message-ID: <1j7bqhtkyt.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On mer. 08 avril 2026 at 22:32, Chuan Liu wrote: > Hi Krzysztof (& ALL), > Thanks for review. > > On 2/9/2026 9:17 PM, Krzysztof Kozlowski wrote: >> [ EXTERNAL EMAIL ] >> On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote: >>> From: Chuan Liu >>> >>> Implement core clock driver for Amlogic SoC platforms, supporting >> So how did all existing Amlogic SoC platforms work so far without basic >> clock driver? Really, how? >> You are suppose to grow existing code, not add your completely new >> "basic" driver just because you have it that way in downstream. >> > > Firstly, apologies for the delayed response. I had intended to consolidate > the V1 review feedback and come back with a clearer plan for V2 changes. In > the meantime, Martin has provided many detailed and valuable suggestions - > much appreciated. > > The original goal of optimizing the HW based on A9 and introducing a new > clock driver is to reduce unnecessary complexity in the driver. On A9, we > optimized the Clock/PLL controller HW to simplify driver performance, > complexity, memory footprint, and reusability. Improvements on the HW side > can also help drive corresponding enhancements in the driver: > - Performance: Encapsulates sub-clock functions, reducing call paths > - Complexity: Standardized register bits eliminate a large number of > bit definitions (~1/3 of original code is defined register bit [1]) > - Memory: Object-oriented design avoids copy/paste for repeated clocks > - Reusability: Same controller works across SoCs without driver > changes (or with minimal changes) > > The old meson driver required compromises to unify legacy controller > characteristics and driver styles. On A9, we want a fresh start. I thought I was clear on the cover letter, apparently not. *This is not going to happen* You've provided no technical justification for such "a fresh start". There no reason for A9 HW to be supported by different drivers than the rest of the Amlogic SoC when it is quite clear it can fit with the current drivers. At lot of work by a lot of different people has gone into stabilizing and maintaing the current driver. That's valuable too. If you are not happy with current level of "performance" then make your case with actual numbers and submit changes against the current drivers, making improvement available to all supported SoCs. That's how upstream works. > >> Best regards, >> Krzysztof -- Jerome