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Thu, 30 Oct 2025 01:38:30 -0700 (PDT) From: Jerome Brunet To: Chuan Liu via B4 Relay Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , chuan.liu@amlogic.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, da@libre.computer Subject: Re: [PATCH v2 4/5] clk: amlogic: Optimize PLL enable timing In-Reply-To: <20251030-optimize_pll_driver-v2-4-37273f5b25ab@amlogic.com> (Chuan Liu via's message of "Thu, 30 Oct 2025 13:24:14 +0800") References: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com> <20251030-optimize_pll_driver-v2-4-37273f5b25ab@amlogic.com> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Thu, 30 Oct 2025 09:38:29 +0100 Message-ID: <1ja518zsvu.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu 30 Oct 2025 at 13:24, Chuan Liu via B4 Relay wrote: > From: Chuan Liu > > l_detect controls the enablement of the PLL lock detection module. > It should remain disabled while the internal PLL circuits are > reaching a steady state; otherwise, the lock signal may be falsely > triggered high. > > Before enabling the internal power supply of the PLL, l_detect should > be disabled. After the PLL=E2=80=99s internal circuits have stabilized, > l_detect should be enabled to prevent false lock signal triggers. You to reformat this description. It feel that both paragraph are saying the same thing. > > Currently, only A1 supports both l_detect and current_en, so this > patch will only affect A1. > > Signed-off-by: Chuan Liu > --- > drivers/clk/meson/clk-pll.c | 28 +++++++++++++++------------- > 1 file changed, 15 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index 6c794adb8ccd..c6eebde1f516 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c > @@ -383,36 +383,38 @@ static int meson_clk_pll_enable(struct clk_hw *hw) > if (MESON_PARM_APPLICABLE(&pll->rst)) > meson_parm_write(clk->map, &pll->rst, 1); >=20=20 > + /* Disable the PLL lock-detect module */ > + if (MESON_PARM_APPLICABLE(&pll->l_detect)) > + meson_parm_write(clk->map, &pll->l_detect, 1); > + > /* Enable the pll */ > meson_parm_write(clk->map, &pll->en, 1); > /* Wait for Bandgap and LDO to power up and stabilize */ > udelay(20); >=20=20 > - /* Take the pll out reset */ > - if (MESON_PARM_APPLICABLE(&pll->rst)) > - meson_parm_write(clk->map, &pll->rst, 0); Why is the reset moving around ? nothing is said in the description about that > - > - /* Wait for PLL loop stabilization */ > - udelay(20); > - > /* > * Compared with the previous SoCs, self-adaption current module > * is newly added for A1, keep the new power-on sequence to enable the > * PLL. The sequence is: > - * 1. enable the pll, delay for 10us > + * 1. enable the pll, delay for 20us > * 2. enable the pll self-adaption current module, delay for 40us > * 3. enable the lock detect module > */ > if (MESON_PARM_APPLICABLE(&pll->current_en)) { > - udelay(10); > meson_parm_write(clk->map, &pll->current_en, 1); > - udelay(40); > + udelay(20); > } >=20=20 > - if (MESON_PARM_APPLICABLE(&pll->l_detect)) { > - meson_parm_write(clk->map, &pll->l_detect, 1); > + /* Take the pll out reset */ > + if (MESON_PARM_APPLICABLE(&pll->rst)) > + meson_parm_write(clk->map, &pll->rst, 0); > + > + /* Wait for PLL loop stabilization */ > + udelay(20); > + > + /* Enable the lock-detect module */ > + if (MESON_PARM_APPLICABLE(&pll->l_detect)) > meson_parm_write(clk->map, &pll->l_detect, 0); > - } >=20=20 > if (meson_clk_pll_wait_lock(hw)) { > /* disable PLL when PLL lock failed. */ --=20 Jerome