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[82.243.161.21]) by smtp.gmail.com with ESMTPSA id s11sm2217128edh.17.2020.08.29.07.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Aug 2020 07:17:39 -0700 (PDT) References: <577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Stefan Agner , narmstrong@baylibre.com Cc: mturquette@baylibre.com, sboyd@kernel.org, khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Marek Szyprowski , Anand Moon Subject: Re: [PATCH v2] clk: meson: g12a: mark fclk_div2 as critical In-reply-to: <577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch> Date: Sat, 29 Aug 2020 16:17:35 +0200 Message-ID: <1ja6yd7czk.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 28 Aug 2020 at 17:52, Stefan Agner wrote: > On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2 > seems to be necessary for the system to operate correctly as well. > > Typically, the clock also gets chosen by the eMMC peripheral. This > probably masked the problem so far. However, when booting from a SD > card the clock seems to get disabled which leads to a system freeze. > > Let's mark this clock as critical, fixing boot from SD card on G12b > platforms. > > Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") > Cc: Marek Szyprowski > Signed-off-by: Stefan Agner > Tested-by: Anand Moon Applied Thx. > --- > drivers/clk/meson/g12a.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index fad616cac01e..6d44cadc06af 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -298,6 +298,17 @@ static struct clk_regmap g12a_fclk_div2 = { > &g12a_fclk_div2_div.hw > }, > .num_parents = 1, > + /* > + * Similar to fclk_div3, it seems that this clock is used by > + * the resident firmware and is required by the platform to > + * operate correctly. > + * Until the following condition are met, we need this clock to > + * be marked as critical: > + * a) Mark the clock used by a firmware resource, if possible > + * b) CCF has a clock hand-off mechanism to make the sure the > + * clock stays on until the proper driver comes along > + */ > + .flags = CLK_IS_CRITICAL, > }, > };