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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y20sm7513220wmi.25.2020.02.05.04.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2020 04:18:23 -0800 (PST) References: User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Nicolas Belin , linus.walleij@linaro.org Cc: Kevin Hilman , linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] pinctrl: meson-gxl: fix GPIOX sdio pins In-reply-to: Date: Wed, 05 Feb 2020 13:18:22 +0100 Message-ID: <1ja75x6xdd.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 05 Feb 2020 at 12:22, Nicolas Belin wrote: > In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused > any issue so far because devices using these pins always take both pins > so the resulting configuration is OK. > > Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") > Signed-off-by: Nicolas Belin Reviewed-by: Jerome Brunet > --- > drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c > b/drivers/pinctrl/meson/pinctrl-meson-gxl.c > index 72c5373c8dc1..e8d1f3050487 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c > +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c > @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; > static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; > static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; > static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; > -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; > -static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; > +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; > +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; > static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; > > static const unsigned int nand_ce0_pins[] = { BOOT_8 };